EP80579 Datasheet, PDF (143/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Section 5.3.3, Section 5.3.4, Section 5.3.5, Section 5.3.6, Section 5.3.7, and
Section 5.3.8 discuss the specific per-unit events that the IMCH hardware captures and
rolls up into the global conditions that Table 5-1 lists.
5.3.3
Unit-Level Errors from the Buffer Unit
The IMCH buffer unit captures error events from the memory system coherent Posted
Memory Write Buffer (PMWB) in the BUF_FERR and BUF_NERR registers. The buffer
unit reports an error event to the IA-32 core through SCI, SMI, SERR, or MCERR signals
based on the settings in the BUF_SCICMD, BUF_SMICMD, BUF_SERRCMD, and
BUF_MCERRCMD registers. Software can independently configure the specific signal
that each buffer unit error event uses.
.
Table 5-2.
Table 5-2 summarizes the error conditions that the PMWB can generate.
Summary of IMCH Buffer Unit Error Conditions
Event
Type
Fatality^a
Reports via^b
Notes
DRAM to PMWB
Parity
System Bus or I/O
to PMWB Parity
PMWB to System
Bus Parity
PMWB to DRAM
Parity
Uncorrectable
Uncorrectable
Uncorrectable
Uncorrectable
Non-Fatal
Non-Fatal
Non-Fatal
Non-Fatal
SCI, MCERR, Parity error detected on read from
SMI, or SERR DRAM agent by PMWB.
SCI, MCERR, Parity error detected on write to PMWB
SMI, or SERR from system bus or I/O agent.
SCI, MCERR, Parity error detected on data to the
SMI, or SERR system bus.
SCI, MCERR, Parity error detected when PMWB is
SMI, or SERR flushed to DRAM.
a. Fatal versus non-fatal classification for reporting through GLOBAL_FERR and GLOBAL_NERR.
b. Based on BUF_SCICMD, BUF_SMICMD, BUF_SERRCMD, and BUF_MCERRCMD register values.
Table 5-3 summarizes the capabilities of the IMCH buffer unit error handling for each of
the features that the unit is expected to provide.
Table 5-3. Summary of IMCH Buffer Unit Error Reporting Capabilities
Feature
Implementation
Enabling and
Masking Error
Reporting
The BUF_EMASK (see Section 16.2.1.29, “Offset 74h: BUF_EMASK - Memory Buffer Error
Mask Register”), BUF_SCICMD, BUF_SMICMD, BUF_SERRCMD, and BUF_MCERRCMD
registers enable and mask error reporting.
The PCICMD register (see Section 16.2.1.3, “Offset 04h: PCICMD - PCI Command
Register”) also enables and masks SERR signals.
Logging Details
IMCH does not capture error logging information beyond the event flags in the BUF_FERR,
BUF_NERR and PCISTS (see Section 16.2.1.4, “Offset 06h: PCISTS - PCI Status Register”)
registers.
Reporting Multiple The BUF_NERR register captures “next” errors. This register indicates up to one additional
Errors
error (beyond the first error) of each type.
Data Poisoning IMCH passes along error information to poison data.
5.3.4
Unit-Level Errors from the DRAM Interface
These errors include the error events reported by the memory controller, see Section
5.5, “Error Reporting by the System Memory Controller” on page 153 for additional
details.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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