EP80579 Datasheet, PDF (837/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
23.1.4.2 Offset 82h: MC – Message Signaled Interrupt Message Control
Register
Table 23-29. Offset 82h: MC – Message Signaled Interrupt Message Control Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:2
Offset Start: 82h
Offset End: 83h
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
15 : 08
07
Bit Acronym
Bit Description
Sticky
Reserved
C64
Reserved
64 Bit Address Capable (C64): Capable of generating a
32-bit message only.
Multiple Message Enable (MME): When this field is
cleared to ‘000’ (and MSIE is set), only a single MSI
message will be generated for all SATA ports, and bits
[15:0] of the message vector will be driven from
MD[15:0].
Bit Reset
Value
0h
0h
Bit Access
RO
RO
06 : 04
03 : 01
00
MME
MMC
MSIE
MME
Value Driven on MSI Memory Write
Bits[15:2]
Bit[1]
Bit[0]
000
001
010
011–111
MD[15:2]
Reserved
Reserved
MD[1]
Reserved
Reserved
Reserved
MD[0]
Reserved
Reserved
Values ‘011b’ to ‘111b’ are reserved. If this field is set to
one of these reserved values, the results are undefined.
Multiple Message Capable (MMC): Indicates the
number of interrupt message supported by SATA
controller.
000: 1 MSI Capable
001: Reserved010: Reserved 100: Reserved
MSI Enable (MSIE): If set, MSI is enabled and
traditional interrupt pins are not used to generate
interrupts.
000h
RW
000h
0h
RWO
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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