EP80579 Datasheet, PDF (949/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
25.1.1.15 USBLKMCR - USB Legacy Keyboard/Mouse Control Register
This register is implemented separately in each of the USB1.1 functions. However, the
enable and status bits for the trapping logic are ORed and shared, respectively, since
their functionality is not specific to any one host controller.
Table 25-16. USBLKMCR - USB Legacy Keyboard/Mouse Control Register (Sheet 1 of 2)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:29:0
Offset Start: C0h
Offset End: C1h
Size: 16 bit
Default: 2000h
Power Well: Core
Bit Range
15
14
13
12
11
10
Bit Acronym
Bit Description
Sticky
SMIBYENDPS
SMI Caused by End of Pass-through: Indicates if the
event occurred. Even if the corresponding enable bit is not
set in the Bit 7, then this bit will still be active. It is up to
the SMM code to use the enable bit to determine the exact
cause of the SMI#.
0 = No event occurred.
1 = Event occurred.
Note: Writing a 1 to this bit (in any of the controllers)
will clear the latch.
Reserved Reserved
USBPIRQEN
PCI Interrupt Enable: Used to prevent the USB controller
from generating an interrupt due to transactions on its
ports. When disabled, that it will probably be configured to
generate an SMI using bit 4 of this register. Defaults to 1
for compatibility with older USB software.
0 = Disable
1 = Enable
SMIBYUSB
SMI Caused by USB Interrupt: This bit indicates if an
interrupt event occurred from this classic controller. The
interrupts from the classic USB controller is taken before
the enable in bit 13 has any effect to create this read-only
bit. Even if the corresponding enable bit is not set in the Bit
4, then this bit may still be active. It is up to the SMM code
to use the enable bit to determine the exact cause of the
SMI#.
0 = No event occurred
1 = Event occurred.
Note: Writing a 1 to this bit will have no effect. The
software must clear the interrupts via the USB
controllers.
TRAPBY64W
SMI Caused by Port 64 Write: Indicates if the event
occurred. Even if the corresponding enable bit is not set in
the Bit 3, then this bit will still be active. It is up to the
SMM code to use the enable bit to determine the exact
cause of the SMI#. Writing a 1 to this bit (in any of the
controllers) will clear the bit. The A20Gate Pass-Through
Logic allows specific port 64h Writes to complete without
setting this bit.
0 = No event occurred.
1 = Event Occurred.
Note: Software clears this bit by writing a 1 to the bit
location in any of the controllers
TRAPBY64R
SMI Caused by Port 64 Read: Indicates if the event
occurs. Even if the corresponding enable bit is not set in
the Bit 2, then this bit will still be active. It is up to the
SMM code to use the enable bit to determine the exact
cause of the SMI#. Writing a 1 to this bit (in any of the
controllers) will clear the bit.
0 = No event occurred.
1 = Event Occurred.
Note: Software clears this bit by writing a 1 to the bit
location in any of the controllers
Bit Reset
Value
0h
0h
1
0h
0h
0h
Bit Access
RWC
RW
RO
RWC
RWC
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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