EP80579 Datasheet, PDF (67/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Contents
18-7
18-8
18-9
18-10
18-11
18-12
18-13
18-14
18-15
19-1
19-2
19-3
19-4
19-5
19-6
19-7
19-8
19-9
19-10
19-11
19-12
19-13
19-14
19-15
19-16
19-17
19-18
19-19
19-20
19-21
19-22
19-23
19-24
19-25
19-26
19-27
19-28
19-29
19-30
19-31
19-32
19-33
20-1
20-2
20-3
20-4
20-5
20-6
20-7
20-8
20-9
Offset 08h: TCTL1 - TCO 1 Control Register ....................................................... 720
Offset 0Ah: TCTL2 - TCO 2 Control Register ....................................................... 721
Offset 0Ch: TMSG[1-2] - TCO MESSAGE Register ............................................... 721
Offset 0Eh: TWDS - TCO Watchdog Status Register ............................................ 722
Offset 10h: LE - Legacy Elimination Register ...................................................... 722
Offset 12h: TTMR - TCO Timer Initial Value Register ........................................... 723
Event Transitions that Cause Messages .............................................................. 728
SMBus Message Format .................................................................................... 731
Message Address Byte ...................................................................................... 732
Bus 0, Device 31, Function 0: Summary of LPC Interface PCI Configuration Registers 733
Offset 00h: ID: Vendor Identification Register ...................................................... 734
Offset 04h: CMD: Device Command Register ....................................................... 735
Offset 06h: STS: Status Register ....................................................................... 736
Offset 08h: RID: Revision ID Register ................................................................. 737
Offset 09h: CC: Class Code Register .................................................................. 737
Offset 0Dh: MLT: Master Latency Timer Register ................................................. 737
Offset 0Eh: HTYPE: Header Type Register ........................................................... 738
Offset 2Ch: SID: Subsystem Identifiers Register .................................................. 738
Offset 40h: ABASE: ACPI Base Address Register .................................................. 739
Offset 44h: ACTL: ACPI Control Register ............................................................ 739
Offset 48h: GBA: GPIO Base Address Register ..................................................... 740
Offset 4Ch: GC: GPIO Control Register ............................................................... 741
Offset 60h: PARC: PIRQA Routing Control Register ............................................. 741
Offset 61h: PBRC: PIRQB Routing Control Register .............................................. 742
Offset 62h: PCRC: PIRQC Routing Control Register .............................................. 742
Offset 63h: PDRC: PIRQDQ Routing Control Register ............................................ 743
Offset 64h: SCNT: Serial IRQ Control Register...................................................... 744
Offset 68h: PERC: PIRQEQ Routing Control Register ............................................ 745
Offset 69h: PFRC: PIRQF Routing Control Register .............................................. 745
Offset 6Ah: PGRC: PIRQG Routing Control Register ............................................. 746
Offset 6Bh: PHRC: PIRQH Routing Control Register ............................................. 747
Offset 80h: IOD: I/O Decode Ranges Register ..................................................... 747
Offset 82h: IOE: I/O Enables Register ................................................................ 749
Offset 84h: LG1: LPC Generic Decode Range 1 Register ........................................ 750
Offset 88h: LG2: LPC Generic Decode Range 2 Register ........................................ 751
Offset D0h: FS1: FWH ID Select 1 Register ......................................................... 752
Offset D4h: FS2: FWH ID Select 2 Register ......................................................... 753
Offset D8h: FDE: FWH Decode Enable Register .................................................... 754
Offset DCh: BC: BIOS Control Register ............................................................... 756
Offset F0h: RCBA: Root Complex Base Address Register ....................................... 757
Offset F8h: MANID: Manufacturer ID Register .................................................... 757
LPC Cycle Types Supported .............................................................................. 759
Summary of LPC DMA Registers Mapped in I/O Space ........................................... 764
0000h (IO) Base Address Registers in the IA F1 View ............................................ 764
0000h (IO) Base Address Registers in the IA F2 View ............................................ 765
Offset 00h: DMA_BCA[0-3] - DMA Base and Current Address
Registers for Channels 0-3 .............................................................................. 766
Offset C4h: DMA_BCA[5-7] - DMA Base and Current Address
Registers for Channels 5-7 .............................................................................. 767
Offset 01h: DMA_BCC[0-3] - DMA Base and Current Count
Registers for Channels 0-3 ................................................................................ 768
Offset C6h: DMA_BCC[5-7] - DMA Base and Current Count
Registers for Channels 5-7 ................................................................................ 769
Offset 08h: DMA_COMMAND - DMA Command Register ........................................ 770
Offset 87h: DMA_MPL[0-3] - DMA Memory Low Page Registers for Channels 0-3 ...... 771
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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