EP80579 Datasheet, PDF (679/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.7
Warning:
Note:
Memory Mapped I/O for NSI Registers
This section describes the memory-mapped registers for the North South Interface
(NSI). The NSIBAR register, described in Section 16.1, “IMCH Registers: Bus 0, Device
0, Function 0” provides the base address for these registers. The offsets listed for the
following registers are relative to this base address.
This Root Complex Register Block (RCRB) controls CMI’s internal serial interconnect
bus..
Address locations that are not listed are considered reserved register locations. Reads
to reserved registers may return non-zero values. Writes to reserved locations may
cause system failure.
Reserved bits are Read Only.
Table 16-347.Bus 0, Device 0, Function 0: Summary of IMCH Configuration Registers
Mapped Through NSIBAR Memory BAR
Offset Start Offset End
Register ID - Description
00h
04h
08h
0Ch
10h
14h
1Ah
80h
84h
03h
07h
0Bh
0Dh
13h
17h
1Bh
83h
87h
“Offset 00h: SNSIVCECH - NSI Virtual Channel Enhanced Capability Header
Register” on page 680
“Offset 04h: NSIPVCCAP1 - NSI Port VC Capability Register 1” on page 680
“Offset 08h: NSIPVCCAP2 - Port VC Capability Register 2” on page 681
“Offset 0Ch: NSIPVCCTL - NSI Port VC Control Register” on page 682
“Offset 10h: NSIVC0RCAP - NSI VC0 Resource Capability Register” on page 682
“Offset 14h: NSIVC0RCTL - NSI VC0 Resource Control Register” on page 683
“Offset 1Ah: NSIVC0RSTS - NSI VC0 Resource Status Register” on page 684
“Offset 80h: NSIRCILCECH - NSI Root Complex Internal Link Control Enhanced
Capability Header Register” on page 684
“Offset 84h: NSILCAP - NSI Link Capabilities Register” on page 685
Default
Value
04010002h
00000000h
00000001h
0000h
00000001h
800000FFh
0002h
00010006h
0003A041h
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
679