EP80579 Datasheet, PDF (1748/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 48-11. General-Purpose IO Signals (Sheet 5 of 5)
Signal Name
IO Type
GP41_LDRQ[1]# LVTTL,3.3V
GP26_SATA0GP
LVTTL,3.3V
GP29_SATA1GP
LVTTL,3.3V
GP11_SMBALERT
#
LVTTL,3.3V
TOTAL
Direction
Ball
Count
External
Pull-Up/
Down
[Ohms]
BSC/
XOR
Signal Description Normal/Alternate Mode
I
1
BSC
LPC Serial DMA/Master Request Input Bit 1:
Used by LPC devices, such as Super I/O chips,
to request DMA or bus master access.This signal
is typically connected to external Super I/O
device.
Note: Internal pullup is always enabled (50K
nominal).
GP41_LDRQ1# may optionally be used as
GPI[41].
Serial ATA Port 0 General Purpose: This input pin
can be configured as an interlock switch for
SATA Port 0 or as a general purpose input,
depending on the platform needs.
I
1
BSC
When used as an interlock switch status
indication, this signal must be driven to '0' to
indicate that the switch is closed, and to '1' to
indicate that the switch is open. If interlock
switches are not required, the platform can
configure this signal as GPI[26].
Note: GP26_SATA0GP and GP29_SATA1GP must
be configured for the same purpose (i.e., either
both SATAxGP or both GPIO functionality).
Serial ATA Port 1 General Purpose: Same
function as GP26_SATA0GP, except for SATA Port
1.
I
1
BSC
When used as an interlock switch status
indication, this signal must be driven to '0' to
indicate that the switch is closed, and to '1' to
indicate that the switch is open. If interlock
switches are not required, the platform can
configure this signal as GPI[29].
Note: GP26_SATA0GP and GP29_SATA1GP must
be configured for the same purpose (i.e., either
both SATAxGP or both GPIO functionality).
SMBus Alert: This signal is used to wake the
system or generate an SMI.
10K Up (in
I
1
SMBALERT BSC Note that the platform can also elect to use this
mode)
signal as GPI[11] if SMBALERT functionality is
not needed. When this signal is used as
SMBALERT#, an external pull-up is required.
36
Table 48-12. IICH Interrupt Signals (Sheet 1 of 2)
Signal Name
GP5_PIRQH#
GP4_PIRQG#
GP3_PIRQF#
IO Type
Direction
Ball
Count
External
Pull-Up/
Down
[Ohms]
BSC/
XOR
Signal Description Normal/Alternate Mode
See GPIO interface.
See GPIO interface.
See GPIO interface.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1748
August 2009
Order Number: 320066-003US