EP80579 Datasheet, PDF (1439/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 37-25. CTRL: Device Control Register (Sheet 2 of 3)
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 0000h
Offset End: 0003h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 0000h
Offset End: 0003h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 0000h
Offset End: 0003h
Size: 32 bits
Default: 00000A09h
GbE0: Aux
Power Well: Gbe1/2:
Core
Bit Range
26
25 :21
20
Bit Acronym
Bit Description
Sticky
RST
Rsvd
ADVD3WUC
Device Reset, also referred to as a “Soft Reset”. Normally
0, writing 1 initiates the reset. This bit is self clearing.
CTRL.RST may be used to globally reset the entire GbE
hardware. This register is provided primarily as a last-ditch
software mechanism to recover from an indeterminate or
suspected hung hardware state. Most registers (receive,
transmit, interrupt, statistics, etc.), and state machines
will be set to their power-on reset values, approximating
the state following a power-on or Unit Reset. However, the
Packet Buffer Allocation Register (PBA) retains its value
through a global reset.
Note: Software must first disable both transmit & receive
operation using the TCTL.EN and RCTL.EN register
bits before asserting CTRL.RST. To ensure that the
global device reset has fully completed and that
the controller will respond to subsequent
accesses, software must wait a minimum of 5
milliseconds after setting CTRL.RST before
attempting to check if the bit has cleared or to
access any other GbE device register.
Reserved
D3Cold WakeUp Capability Advertisement Enable.
When set, D3Cold wakeup capability may be advertised
based on whether the AUX_PWR pin advertises presence of
auxiliary power (see section 2.13.3 for details). When 0,
D3Cold wakeup capability will not be advertised even if
AUX_PWR presence is indicated. Formerly used as SDP2
pin data value, initial value is EEPROM-configurable
Bit Reset
Value
0h
0h
0h
Bit Access
RW
RV
RW
19 : 13
12
11
10
Rsvd
FRCDPLX
FRCSPD
Rsvd
*Note that this bit is loaded from the EEPROM, if present
Reserved
Force Duplex.
0 = Mode is Full-Duplex, regardless of the FD setting.
1 = CTRL.FD bit sets duplex mode.
Force Speed.
0 = Default of 1Gbps is used to set the MAC speed. See
“Physical Layer Auto-Negotiation & Link Setup
Features” on page 1394 for more details.
1 = CTRL.SPEED bits set the MAC speed.
Note: This bit is superseded by the CTRL_EXT.SPD_BYPS
bit which has a similar function.
Note: *Note that this bit is loaded from the EEPROM, if
present
Reserved
0h
RV
0h
RW
1
RW
0h
RV
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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