EP80579 Datasheet, PDF (1245/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
35.6.1.7
Offset 08h: RID – Revision ID Register
The value of this register comes from the ICH Compatibility Rev ID registers.
Table 35-12. Offset 08h: RID: Revision ID Register
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: M:0:0
Offset Start: 08h
Offset End: 08h
View: PCI 2
BAR: Configuration
Bus:Device:Function: M:1:0
Offset Start: 08h
Offset End: 08h
View: PCI 3
BAR: Configuration
Bus:Device:Function: M:2:0
Offset Start: 08h
Offset End: 08h
Size: 8 bit
Default: Variable
Power Well: Core
Bit Range
07 : 00
Bit Acronym
Bit Description
Sticky
Revision Identification Number: This value indicates
the revision identification number for the AIOC Device.
RID
The 4 most significant bits are always 0. The 4 least
significant bits follow the ICH revision ID scheme as
defined in Section 19.2.1.4, “Offset 08h: RID - Revision ID
Register” on page 736.
Bit Reset
Value
Variable
Bit Access
RO
35.6.1.8 Offset 09h: CC – Class Code Register
Table 35-13. Offset 09h: CC: Class Code Register
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: M:0:0
Offset Start: 09h
Offset End: 0Bh
View: PCI 2
BAR: Configuration
Bus:Device:Function: M:1:0
Offset Start: 09h
Offset End: 0Bh
View: PCI 3
BAR: Configuration
Bus:Device:Function: M:2:0
Offset Start: 09h
Offset End: 0Bh
Size: 24 bit
Default: 020000h
Power Well: Core
Bit Range
23 : 00
Bit Acronym
Bit Description
Sticky
Class Code: This value indicates the base class, subclass,
CC
and interface.
020000h = Network Controller / Ethernet controller
Bit Reset
Value
020000h
Bit Access
RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1245