EP80579 Datasheet, PDF (528/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.4.1.3 Offset 02h: DID - Device Identification Register
Table 16-142.Offset 02h: DID - Device Identification Register
Description:
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 02h
Offset End: 03h
Size: 16 bit
Default: 5025h
Power Well: Core
Bit Range Bit Acronym
Bit Description
15 : 00
DID
Device Identification Number: This is a 16-bit value
assigned to the IMCH Device 3, Function 0.
Sticky
Bit Reset
Value
Bit Access
5025h
RO
16.4.1.4
Offset 04h: PCICMD - PCI Command Register
Many of these bits are not applicable since the primary side of this device is not an
actual PCI bus.
Table 16-143.Offset 04h: PCICMD - PCI Command Register (Sheet 1 of 2)
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 04h
Offset End: 05h
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 04h
Offset End: 05h
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
15 : 11
10
09
08
07
Bit Acronym
Bit Description
Sticky
Reserved
INTXD
FB2B
SERRE
ADSTEP
Reserved.
INTx Assertion DIsable: Controls the ability of thePCI
Express* device to assert INTx interrupts. When set,
devices are prevented from asserting INTx. This bit only
applies to legacy interrupts and not MSIs. Also this bit has
no affect on PCI Express* messages that are converted to
legacy interrupts. These are only internal, device
generated interrupts.
0 = Enable INTx assertion
1 = Disable INTx assertion
Fast Back-to-Back Enable: Not Applicable-hardwired to
0.
SERR Enable: This bit is a global enable bit for Device
SERR messaging. The IMCH does not have an SERR#
signal. The IMCH communicates the SERR# condition by
sending an SERR message to the IICH via NSI.
0 = No SERR message is generated by the IMCH for
Device (unless enabled through enhanced
configuration registers).
1 = Enable SERR, SCI, or SMI messages or asserting
MCERR# for specific Device error conditions.
Address/Data Stepping: Not applicable.
Bit Reset
Value
00h
0b
0b
0b
0b
Bit Access
RW
RO
RW
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
528
August 2009
Order Number: 320066-003US