EP80579 Datasheet, PDF (972/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 25-31. Data Field
x+5
x+6
x+7
x+8
Byte N, D5
Byte N, D6
Byte N, D7
Byte N+1, D 0
25.8.7
Cyclic Redundancy Check (CRC)
CRC is used to protect the all non-PID fields in token and data packets. In this context,
these fields are considered to be protected fields. Full details on this are given in the
USB Specification.
25.9
Packet Formats
The USB protocol calls out several packet types: token, data, and handshake packets.
Full details on this are given in the USB Specification.
25.10 USB Interrupts
25.10.1
Overview
There are two general groups of USB interrupt sources, those resulting from execution
of transactions in the schedule, and those resulting from a CMI operation error. All
transaction-based sources can be masked by software through the Interrupt Enable
register. Additionally, individual transfer descriptors can be marked to generate an
interrupt on completion.
When the CMI drives an interrupt for USB, it internally drives the PIRQA# pin for USB
function #0(see Chapter 26.0, “USB 2.0 Host Controller: Bus 0, Device 29, Function 7”)
until all sources of the interrupt are cleared. In order to accommodate some operating
systems, the Interrupt Pin register must contain a different value for each function of
this multi-function device.
25.10.2
Transaction-Based Interrupts
These interrupts are not signaled until after the status for the last complete transaction
in the frame has been written back to host memory. This guarantees that software can
safely process through (Frame List Current Index -1) when it is servicing an interrupt.
25.10.2.1 CRC Error/Time-out
A CRC/Time-out error occurs when a packet transmitted from the CMI to a USB device
or a packet transmitted from a USB device to the CMI generates a CRC error. The CMI
is informed of this event by a time out from the USB device or by the CMI’s CRC
checker generating an error on reception of the packet. Additionally, a USB bus time-
out occurs when USB devices do not respond to a transaction phase within 19 bit times
of an EOP. Either of these conditions will cause the C_ERR field of the TD to be
decremented.
When the C_ERR field decrements to zero, the following occurs:
• The Active bit in the TD is cleared
• The Stalled bit in the TD is set
• The CRC/Time-out bit in the TD is set.
Intel^® EP80579 Integrated Processor Product Line Datasheet
972
August 2009
Order Number: 320066-003US