EP80579 Datasheet, PDF (1642/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 41-12. Offset 0004h: TS_Event Register (Sheet 2 of 2)
Description:
View: PCI
BAR: CSRBAR
Bus:Device:Function: M:7:0
Offset Start: 00000004h
Offset End: 00000007h
Size: 32 bits
Default: 0022h
Power Well: Core
Bit Range
2: 2
1: 1
0: 0
Bit
Acronym
Bit Description
Sticky
sns
ttipend
RSVD
ASMS Snapshot. This event bit sets when the system time
register value is captured in the Auxiliary Slave Mode
Snapshot register upon detection of a active high level on a
general purpose input, asmssig.
• When this signal is asserted high, an interrupt will be
generated to the Host on the shared interrupt signal
(ts_ntreq) if the asm bit in the Time Sync Control register
is set.
• To clear the sns bit, write a ‘1’ to it.
Target Time Interrupt Pending. This bit is the Target Time
interrupt pending indication. When this bit is set, it indicates
that the Target Time interrupt condition has occurred, which
means that the System Time value has reached the 64-bit
Target Time register value.
• If ttm in the Time Sync Control register is set, the
interrupt will be passed to the Host processor.
• To clear this condition, the firmware must write a ‘1’ to
the ttipend bit.
To prevent an immediate reoccurrence of the target time
interrupt, the processor should first write a new value to the
Target Time register and then clear the condition. This bit is
set at power-up since both the System Time and the Target
Time are reset at power-up to 0.
Reserved for future use.
Bit Reset
Value
0h
1
0h
Bit Access
RWC
RWC
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
1642
August 2009
Order Number: 320066-003US