EP80579 Datasheet, PDF (41/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Contents
37.6.3.4 IMS0 – Interrupt 0 Mask Set/Read Register .......................................1459
37.6.3.5 IMC0 – Interrupt 0 Mask Clear Register ...........................................1460
37.6.3.6 ICR1 – Interrupt 1 Cause Read Register............................................1462
37.6.3.7 ICS1 – Interrupt 1 Cause Set Register .............................................1464
37.6.3.8 IMS1 – Interrupt 1 Mask Set/Read Register .......................................1466
37.6.3.9 IMC1 – Interrupt 1 Mask Clear Register ...........................................1467
37.6.3.10 ICR2 – Error Interrupt Cause Read Register ......................................1469
37.6.3.11 ICS2 – Error Interrupt Cause Set Register ........................................1471
37.6.3.12 IMS2 – Error Interrupt Mask Set/Read Register..................................1472
37.6.3.13 IMC2 – Error Interrupt Mask Clear Register ......................................1473
37.6.4 Receive Registers: Detailed Descriptions ..................................................1474
37.6.4.1 RCTL – Receive Control Register ......................................................1474
37.6.4.2 FCRTL: Flow Control Receive Threshold Low Register .........................1478
37.6.4.3 FCRTH – Flow Control Receive Threshold High Register ......................1479
37.6.4.4 RDBAL – Receive Descriptor Base Address Low Register ......................1480
37.6.4.5 RDBAH – Receive Descriptor Base Address High Register ...................1480
37.6.4.6 RDLEN – Receive Descriptor Length Register ....................................1481
37.6.4.7 RDH – Receive Descriptor Head Register ..........................................1481
37.6.4.8 RDT – Receive Descriptor Tail Register .............................................1482
37.6.4.9 RDTR – RX Interrupt Delay Timer (Packet Timer) Register ..................1482
37.6.4.10 RXDCTL – Receive Descriptor Control Register ..................................1483
37.6.4.11 RADV – Receive Interrupt Absolute Delay Timer Register ...................1485
37.6.4.12 RSRPD – Receive Small Packet Detect Interrupt Register.....................1486
37.6.4.13 RXCSUM – Receive Checksum Control Register ..................................1487
37.6.4.14 MTA[0-127] – 128 Multicast Table Array Registers .............................1488
37.6.4.15 RAL[0-15] – Receive Address Low Register........................................1488
37.6.4.16 RAH[0-15] – Receive Address High Register ......................................1489
37.6.4.17 VFTA[0-127] – 128 VLAN Filter Table Array Registers .........................1490
37.6.5 Transmit Registers: Detailed Descriptions .................................................1491
37.6.5.1 TCTL – Transmit Control Register .....................................................1491
37.6.5.2 TIPG – Transmit IPG Register .........................................................1493
37.6.5.3 AIT – Adaptive IFS Throttle Register.................................................1495
37.6.5.4 TDBAL – Transmit Descriptor Base Address Low Register ....................1496
37.6.5.5 TDBAH – Transmit Descriptor Base Address High Register ...................1496
37.6.5.6 TDLEN – Transmit Descriptor Length Register ...................................1497
37.6.5.7 TDH – Transmit Descriptor Head Register..........................................1497
37.6.5.8 TDT – Transmit Descriptor Tail Register ............................................1498
37.6.5.9 TIDV – Transmit Interrupt Delay Value Register .................................1499
37.6.5.10 TXDCTL – Transmit Descriptor Control Register .................................1500
37.6.5.11 TADV – Transmit Absolute Interrupt Delay Value Register ...................1502
37.6.5.12 TSPMT – TCP Segmentation Pad and Minimum Threshold Register ........1503
37.6.6 Statistical Registers: Detailed Descriptions ...............................................1505
37.6.6.1 CRCERRS – CRC Error Count Register ...............................................1505
37.6.6.2 ALGNERRC – Alignment Error Count Register .....................................1506
37.6.6.3 RXERRC – Receive Error Count Register ............................................1506
37.6.6.4 MPC – Missed Packet Count Register ................................................1507
37.6.6.5 SCC – Single Collision Count Register ...............................................1507
37.6.6.6 ECOL – Excessive Collisions Count Register .......................................1508
37.6.6.7 MCC – Multiple Collision Count Register ............................................1508
37.6.6.8 LATECOL – Late Collisions Count Register..........................................1509
37.6.6.9 COLC – Collision Count Register.......................................................1509
37.6.6.10 DC – Defer Count Register ..............................................................1510
37.6.6.11 TNCRS – Transmit with No CRS Count Register ..................................1510
37.6.6.12 CEXTERR – Carrier Extension Error Count Register .............................1511
37.6.6.13 RLEC – Receive Length Error Count Register......................................1511
37.6.6.14 XONRXC – XON Received Count Register ..........................................1512
37.6.6.15 XONTXC – XON Transmitted Count Register ......................................1512
37.6.6.16 XOFFRXC – XOFF Received Count Register ........................................1513
37.6.6.17 XOFFTXC – XOFF Transmitted Count Register ....................................1513
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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