EP80579 Datasheet, PDF (1611/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 40-3. Offset 04h: SSCR1 - SSP Control Register 1 Details (Sheet 2 of 2)
Description:
View: PCI
BAR: CSRBAR
Bus:Device:Function: M:6:0
Offset Start: 04h
Offset End: 07h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
03
02
01
00
Bit Acronym
Bit Description
Sticky
SPO
LBM
TIE
RIE
Motorola SPI SSP_SCLK polarity setting:
0 = The inactive or idle state of SSP_SCLK is low.
1 = The inactive or idle state of SSP_SCLK is high.
Loop Bank Mode Enable bit.
0 = Normal serial port operation enabled
1 = Output of transmit serial shifter connected to input of
receive serial shifter, internally
Transmit FIFO Interrupt Enable
0 = Transmit FIFO level interrupt is disabled
1 = Transmit FIFO level interrupt is enabled
Receive FIFO Interrupt Enable
0 = Receive FIFO level interrupt is disabled
1 = Receive FIFO level interrupt is enabled
Bit Reset
Value
0b
0b
0b
0b
Bit Access
RW
RW
RW
RW
40.4.2.2
40.4.2.3
40.4.2.4
Note:
Receive FIFO Interrupt Enable (RIE)
The Receive FIFO Interrupt Enable (RIE) bit is used to mask or enable the Receive FIFO
service request interrupt. When RIE=0, the interrupt is masked and the state of the
Receive FIFO Service Request (RFS) bit within the SSP Status Register is ignored by the
interrupt controller. When RIE=1, the interrupt is enabled and whenever RFS is set to
one, an interrupt request is made to the interrupt controller. Note that programming
RIE=0 does not affect the current state of RFS or the receive FIFO logic’s ability to set
and clear RFS, it only blocks the generation of the interrupt request.
Transmit FIFO Interrupt Enable (TIE)
The Transmit FIFO Interrupt Enable (TIE) bit is used to mask or enable the transmit
FIFO service request interrupt. When TIE=0, the interrupt is masked and the state of
the Transmit FIFO Service Request (TFS) bit within the SSP Status Register is ignored
by the interrupt controller. When TIE=1, the interrupt is enabled, and whenever TFS is
set to one an interrupt request is made to the interrupt controller. Note that
programming TIE=0 does not affect the current state of TFS or the transmit FIFO
logic’s ability to set and clear TFS, it only blocks the generation of the interrupt request.
Loop Back Mode (LBM)
The loop back mode (LBM) bit is used to enable and disable the ability of the SSP
transmit and receive logic to communicate. When LBM=0, the SSP operates normally.
The transmit and receive data paths are independent and communicate via their
respective pins. When LBM=1, the output of the transmit serial shifter is directly
connected to the input of the receive serial shifter internally.
Loop back mode is only valid for SSP and SPI modes, Microwire mode does not support
loop back mode testing because the bus protocol is half-duplex.
While in loopback mode, the data will continue to be driven on the transmit pins.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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