EP80579 Datasheet, PDF (1861/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 49-35. USB Timing Specifications (Sheet 2 of 2)
Parameter
Min
Max
Units Figure
Notes
High-speed Source
49-20
7
USBp[x], USBn[x] Driver Rise Time
USBp[x], USBn[x] Driver Fall Time
Full-speed Source
0.8
1.2
0.8
1.2
ns
49-20 1, 6 CL = 10 pF
ns
1, 6 CL = 10 pF
8
Source Differential Driver Jitter:
To Next Transition
For Paired Transitions
-25
25
ns
49-21
2, 3
-14
14
ns
Source SE0 interval of EOP
1.25
1.50
µs
4
Source Jitter for Differential Transition to SE0
Transition
-40
100
ns
49-21
5
Receiver Data Jitter Tolerance:
To Next Transition
For Paired Transitions
-152
152
ns
49-21
3
-200
200
ns
EOP Width: Must accept as EOP
670
ns
49-22
4
Width of SE0 interval during differential
transition
210
ns
Notes:
1. Driver output resistance under steady state drive is specified at 28 ohms at minimum and 43 ohms at
maximum.
2. Timing difference between the differential data signals.
3. Measured at crossover point of differential data signals.
4. Measured at 50% swing point of data signals.
5. Measured from last crossover point to 50% swing point of data line at leading edge of EOP.
6. Measured from 10% to 90% of the data signal.
7. High-speed Data Rate has minimum of 479.760 Mb/s and maximum of 480.240 Mb/s
8. Full-speed Data Rate has minimum of 11.97 Mb/s and maximum of 12.03 Mb/s.
9. Low-speed Data Rate has a minimum of 1.48 Mb/s and a maximum of 1.52 Mb/s.
Figure 49-20.USB Rise and Fall Times
Rise Time
Fall Time
C_L
Differential
Data
Lines
10%
90%
90%
10%
C_L
t_R
t_F
Low-speed: 75 ns at C_L = 50 pF, 300 ns at C_L = 350 pF
Full-speed: 4 to 20 ns at C_L = 50 pF
High-speed: 0.8 to 1.2 ns at C_L = 10 pF
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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