EP80579 Datasheet, PDF (1639/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
41.6.1
41.6.1.1
Detailed Register Descriptions
Offset 0000h: TS_Control - Time Sync Control Register
Register
Name
TS_Control
Access
(See below.) Reset Value x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
(Reserved)
Table 41-11. Offset 0000h: TS_Control Register
Description:
View: PCI
BAR: CSRBAR
Bus:Device:Function: M:7:0
Offset Start: 00000000h
Offset End: 00000003h
Size: 32 bits
Default: 00000000h
Power Well: Core
Bit Range
31 : 6
5: 5
4: 4
3: 3
Bit Acronym
Bit Description
Sticky
RSVD
atm
ppsm
amm
Reserved for future use.
Must be written as ‘0’
Auxiliary Target Time Interrupt Mask. The
AuxiliaryTarget Time interrupt mask controls whether the
Auxiliary Target Time interrupt is passed to the Host
processor. When this bit is set, the interrupt to the Host is
enabled. When cleared, the Auxiliary Target Time interrupt
to the Host is disabled.
PPS Interrupt Mask. The PPS interrupt mask controls
whether the 1 PPS Compare register match indication,
which is the pps bit in the Time Sync Event register,
should interrupt the Host processor. When this bit is set,
the interrupt to the Host is enabled. When cleared, the
PPS interrupt to the Host is disabled.
AMMS Interrupt Mask. Controls whether the Auxiliary
Master Mode snapshot indication, which is the snm bit in
the Time Sync Event register, should interrupt the Host
processor.
• When this bit is set, the interrupt to the Host is
enabled.
• When cleared, the AMMS interrupt to the Host is
disabled.
Bit Reset
Value
0
0h
0h
0h
Bit Access
RO
RW
RW
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1639