EP80579 Datasheet, PDF (40/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Contents
37.5.7.4 Packet Format .............................................................................. 1382
37.5.7.5 TCP Segmentation Indication .......................................................... 1383
37.5.7.6 TCP Segmentation Data Descriptors................................................. 1383
37.5.7.7 IP and TCP/UDP Headers ................................................................ 1384
37.5.7.8 Transmit Checksum Off loading with TCP Segmentation...................... 1388
37.5.7.9 IP/TCP/UDP Header Updating.......................................................... 1389
37.5.7.10 Data Flow..................................................................................... 1391
37.5.8 Ethernet Interfaces ............................................................................... 1391
37.5.8.1 MAC/PHY GMII/MII Interface .......................................................... 1392
37.5.8.2 Duplex Operation .......................................................................... 1393
37.5.8.3 Physical Layer Auto-Negotiation & Link Setup Features....................... 1394
37.5.8.4 10/100Mbps Specific Performance Enhancements .............................. 1396
37.5.8.5 Flow Control ................................................................................. 1397
37.5.9 802.1q VLAN Support............................................................................ 1400
37.5.9.1 Transmitting and Receiving 802.1q Packets ...................................... 1401
37.5.9.2 802.1q VLAN Packet Filtering .......................................................... 1401
37.5.10 Wake on LAN ....................................................................................... 1402
37.5.10.1 Advanced Power Management Wakeup............................................. 1402
37.5.10.2 ACPI Power Management Wakeup ................................................... 1403
37.5.10.3 Wake-up Packets: Pre-defined Filters ............................................... 1404
37.5.10.4 Wake-up Packets: Flexible Filters .................................................... 1409
37.5.11 Serial EEPROM ..................................................................................... 1412
37.5.11.1 EEPROM Device............................................................................. 1412
37.5.11.2 Software Accesses......................................................................... 1412
37.5.11.3 Signature Field ............................................................................. 1413
37.5.11.4 EEPROM Map ................................................................................ 1413
37.5.11.5 Hardware Accessed Words.............................................................. 1415
37.5.11.6 Software Accessed Words............................................................... 1417
37.5.12 Error Handling...................................................................................... 1418
37.5.12.1 CSR (Target) Accesses ................................................................... 1418
37.5.12.2 DMA Host (Master) Accesses........................................................... 1418
37.5.12.3 Internal Memories ......................................................................... 1419
37.5.13 Reset Operation ................................................................................... 1420
37.5.13.1 Soft Reset .................................................................................... 1422
37.5.13.2 MAC Disable ................................................................................. 1422
37.5.14 Endianness .......................................................................................... 1422
37.6 GbE Controller Register Summary .................................................................... 1425
37.6.1 Registers Overview ............................................................................... 1425
37.6.1.1 Memory-Mapped Access to Internal Registers and Memories ............... 1436
37.6.1.2 I/O-Mapped Access to Internal Registers and Memories ...................... 1436
37.6.1.3 Register Conventions ..................................................................... 1437
37.6.2 General Registers: Detailed Descriptions.................................................. 1438
37.6.2.1 CTRL – Device Control Register ....................................................... 1438
37.6.2.2 STATUS – Device Status Register .................................................... 1441
37.6.2.3 CTRL_EXT – Extended Device Control Register .................................. 1442
37.6.2.4 CTRL_AUX – Auxiliary Device Control/Status Register ........................ 1444
37.6.2.5 EEPROM_CTRL – EEPROM Control Register ....................................... 1446
37.6.2.6 EEPROM_RR – EEPROM Read Register .............................................. 1448
37.6.2.7 FCAL – Flow Control Address Low Register ........................................ 1449
37.6.2.8 FCAH – Flow Control Address High Register ...................................... 1450
37.6.2.9 FCT – Flow Control Type Register .................................................... 1451
37.6.2.10 VET – VLAN EtherType Register....................................................... 1452
37.6.2.11 FCTTV – Flow Control Transmit Timer Value Register.......................... 1452
37.6.2.12 PBA – Packet Buffer Allocation Register ............................................ 1453
37.6.3 Interrupt Registers: Detailed Descriptions ................................................ 1454
37.6.3.1 ICR0 – Interrupt 0 Cause Read Register ........................................... 1454
37.6.3.2 ITR0 – Interrupt 0 Throttling Register .............................................. 1457
37.6.3.3 ICS0 – Interrupt 0 Cause Set Register ............................................ 1458
Intel^® EP80579 Integrated Processor Product Line Datasheet
40
August 2009
Order Number: 320066-003US