EP80579 Datasheet, PDF (715/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
18.2.1
18.2.2
18.2.2.1
TCO PCI Configuration Registers
See Chapter 19.0, “LPC Interface: Bus 0, Device 31, Function 0.”
Allows setting of the Base Address for the I/O space and routing of the TCO interrupt.
Bus 0, Device 31, Function 0: TCO Configuration Register (I/O-
Mapped via ABASE BAR) Summary Table
The TCO I/O registers reside in a 32-byte range that starts 96 bytes above the power
management (ACPI) I/O space (Section 19.2.2.1, “Offset 40h: ABASE: ACPI Base
Address Register”). Thus TCOBASE (IO) =ABASE (IO) + 60h in the PCI
configuration space. Table 18-2 shows the mapping of the registers within that 32-byte
range. Each register is described in the following sections.
Offset 00h: TRLD - TCO Timer Reload and Current Value Register
Table 18-2. Offset 00h: TRLD - TCO Timer Reload and Current Value Register
Description:
View: PCI
BAR: TCOBASE (IO)
Bus:Device:Function: 0:31:0
Offset Start: 00h
Offset End: 01h
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
15 : 10
09 : 00
Bit Acronym
Bit Description
Sticky
Reserved
TRLD
Reserved.
TCO Timer Value: Reading this register returns the
current count of the TCO timer. Writing any value to this
register reloads the timer to prevent the timeout.
Bit Reset
Value
00h
000h
Bit Access
RO
RW
18.2.2.2 Offset 02h: TDI - TCO Data In Register
Table 18-3. Offset 02h: TDI - TCO Data In Register
Description:
View: PCI
BAR: TCOBASE (IO)
Bus:Device:Function: 0:31:0
Offset Start: 02h
Offset End: 02h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07 : 00
Bit Acronym
Bit Description
Sticky
This data register field is used for passing commands
TDI
from the operating system to the SMI handler. Writes to
this register cause an SMI and set the OS_TCO_SMI bit
in the TCO_STS register (D31, F0, 04h).
Bit Reset
Value
00h
Bit Access
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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