EP80579 Datasheet, PDF (758/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
19.3.1
Overview
The LPC interface is described in the Low Pin Count (LPC) Interface Specification,
Revision 1.1. The LPC interface to the IICH is shown in Figure 19-1. The LPC Controller
implements all of the signals that are shown as optional, but peripherals are not
required to do so.
For the LPC Controller:
• LSMI# can be connected to any of the SMI capable GPIO signals.
• The Super I/O’s PME# can be connected to the PCI PME# signal, however this may
cause software problems. A better choice is to connect it to one of the LPC
Controller’s SCI capable GPIO signals.
• The LPC Controller’s SUS_STAT# signal is connected directly to the LPCPD# signal.
All the other signals have the same name on the LPC Controller and on the LPC
Interface.
Figure 19-1. LPC Interface Diagram
CMI
SUS_STAT#
GPI
PCI Bus
PCICLK PCIRST#
SERIRQ
LAD[3:0]
LFRAME #
LDRQ#
(optiona)l
LPCPD#
(optiona)l
LSLMI#
(optiona)l
Super I/O
PME#
B6464-01
Signal Name
LAD[3:0]
LFRAME#
LDREQ[1:0]#
During
Reset
After
Reset
See
S3
S5
Off
Off
Off
Off
Off
Off
19.3.2
Cycle Types
All of the cycle types implemented are described in the LPC Interface Specification,
Revision 1.1.Table 19-33 shows the supported cycle types.
Intel^® EP80579 Integrated Processor Product Line Datasheet
758
August 2009
Order Number: 320066-003US