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EP80579 Datasheet, PDF (220/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line | |||
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Intel® EP80579 Integrated Processor
7.3.17
LPC DMA
The LPC DMA interface includes the registers listed in Table 7-38 through Table 7-40.
These registers materialize at fixed locations in I/O space. See Chapter 20.0, âLPC
DMAâ for detailed discussion of these registers.
Table 7-38. Summary of LPC DMA Registers Mapped in I/O Space
Offset Start Offset End
Register ID - Description
Default
Value
00h at 02h
C4h at 04h
01h at 02h
C6h at 04h
87h, 83h,
81h, 82h
10h at 02h
C5h at 04h
11h at 02h
C7h at 04h
97h, 93h,
91h, 82h
âOffset 00h: DMA_BCA[0-3] - DMA Base and Current Address Registers for
Channels 0-3â on page 766
XXXX
âOffset C4h: DMA_BCA[5-7] - DMA Base and Current Address Registers for
Channels 5-7â on page 767
XXXX
âOffset 01h: DMA_BCC[0-3] - DMA Base and Current Count Registers for Channels
0-3â on page 768
XXXX
âOffset C6h: DMA_BCC[5-7] - DMA Base and Current Count Registers for Channels
5-7â on page 769
XXXX
âOffset 87h: DMA_MPL[0-3] - DMA Memory Low Page Registers for Channels 0-3â
on page 771
XXXXXXX
8Bh, 89h, 8Ah
9Bh, 99h, 9Ah
âOffset 8Bh: DMA_MPL[5-7]: DMA Memory Low Page Registers for Channels 5-7â
on page 771
XXXXXXX
Table 7-39. 0000h (IO) Base Address Registers in the IA F1 View
Offset Start Offset End
Register ID - Description
08h
18h
08h
18h
0Ah
1Ah
0Bh
1Bh
0Ch
1Ch
0Dh
1Dh
0Eh
1Eh
0Fh
1Fh
08h
18h
08h
18h
0Ah
1Ah
0Bh
1Bh
0Ch
1Ch
0Dh
1Dh
0Eh
1Eh
0Fh
1Fh
âOffset 08h: DMA_COMMAND - DMA Command Registerâ on page 770
âOffset 08h: DMA_COMMAND - DMA Command Registerâ on page 770
âOffset 08h: DMA_STATUS - DMA Status Registerâ on page 772
âOffset 08h: DMA_STATUS - DMA Status Registerâ on page 772
âOffset 0Ah: DMA_WSM - DMA Write Single Mask Registerâ on page 773
âOffset 0Ah: DMA_WSM - DMA Write Single Mask Registerâ on page 773
âOffset 0Bh: DMA_CHM - DMA Channel Mode Registerâ on page 774
âOffset 0Bh: DMA_CHM - DMA Channel Mode Registerâ on page 774
âOffset 0Ch: DMA_CBP - DMA Clear Byte Pointer Registerâ on page 775
âOffset 0Ch: DMA_CBP - DMA Clear Byte Pointer Registerâ on page 775
âOffset 0Dh: DMA_MC - DMA Master Clear Registerâ on page 775
âOffset 0Dh: DMA_MC - DMA Master Clear Registerâ on page 775
âOffset 0Eh: DMA_CM - DMA Clear Mask Registerâ on page 776
âOffset 0Eh: DMA_CM - DMA Clear Mask Registerâ on page 776
âOffset 0Fh: DMA_WAM - DMA Write All Mask Registerâ on page 777
âOffset 0Fh: DMA_WAM - DMA Write All Mask Registerâ on page 777
Default
Value
000X0X00b
000X0X00b
XXXXXXXh
XXXXXXXh
000001xxb
000001xxb
000000XXh
000000XXh
XXXXXXXXh
XXXXXXXXh
XXXXXXXXh
XXXXXXXXh
XXXXXXXXh
XXXXXXXXh
00001111b
00001111b
Intel® EP80579 Integrated Processor Product Line Datasheet
220
August 2009
Order Number: 320066-003US
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