EP80579 Datasheet, PDF (352/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
13.3.5 IMCH Configuration Cycle Flow Chart
Figure 13-5. IMCH Configuration Flow Chart
Access through
memory aperture
DW I/O Write to
Config_Addr
SS with Bit 31=1
I/O Read/Write to
CONFIG_DATA
BUS#=0
IMCH generates
Type 0 Access to Yes
PEA0
IMCH generates
Type 0 Access to Yes
PEA1
IMCH generates
Type 0 Access to
PCI-to-PCI
Yes
Bridge
IMCH generates
Type 1 Access to Yes
PEA0
IMCH generates
Type 1 Access to Yes
PEA1
IMCH generates
Type 1 Access to
PCI-to-PCI
Yes
Bridge
Note:
This path will never be
taken since no bridge will
ever be beneath the
PCI-to-PCI Bridge.
No
BUS#=
Secondary Bus
in IMCH Dev#2
No
BUS#=
Secondary Bus
in IMCH Dev#3
No
BUS#=
Secondary Bus
in IMCH Dev#4
No
BUS# >Sec Bus
BUS# <=Sub Bus
in IMCH Dev#2
No
BUS# >Sec Bus
BUS# <=Sub Bus
in IMCH Dev#3
No
BUS# >Sec Bus
BUS# <=Sub Bus
in IMCH Dev#4
No
IMCH generates
NSI Type 1
Configuration
Cycle
DEVICE#=0
No
IMCH claims if Function=0,
Yes
or 1 and that function is
enabled
DEVICE#=1
No
Yes ^{IMCH claims if Function=0}
and device 1 is enabled
DEVICE#=2
No
Yes ^{IMCH claims if Function=0}
and device 2 is enabled
DEVICE#=3
No
Yes ^{IMCH claims if Function=0}
and device 3 is enabled
DEVICE#=4
Yes ^{IMCH claims if Function=0}
and device 4 is enabled
No
IMCH generates
NSI Type 0
Configuration
Cycle
Intel^® EP80579 Integrated Processor Product Line Datasheet
352
August 2009
Order Number: 320066-003US