EP80579 Datasheet, PDF (1703/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
42.5.2.2 EXP_PARITY_STATUS - Expansion Bus Parity Status Register
Table 42-9. EXP_PARITY_STATUS - Expansion Bus Parity Status Register
Description: Specifies the parity error status.
View: PCI
BAR: CSRBAR
Bus:Device:Function: M:8:0
Offset Start: 00000120h
Offset End: 00000123h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 : 02
01
00
Bit Acronym
Bit Description
Sticky
ErrorAddr
Address corresponding to the parity error
For Outbound transactions, the derivation of this address
is as follows:
• ErrorAddr = Internal_Bus_ADDR[31:5] &
EX_ADDR[4:2]
Internal_BusInternal_BusInternal_BusInternal_BusIf
multiple parity errors occur (eg- multiple parity errors
within a multi-word transfer/burst; or additional parity
errors detected on subsequent transactions), then
ErrorAddr contains the address of the first parity error.
After receiving a parity error, the ErrorAddr is locked until
OutErrorSts is cleared by software.
If another parity error occurs prior to the interrupt and
EXP_PARITY_STATUS being cleared, then the subsequent
parity errors will not be trapped nor will the address be
logged. As a result, only the first errored transaction will
be dropped, but the subsequent (errored) transaction(s)
will be completed.
Note: ErrorAddr will not be unlocked until the current
transaction is complete.
RSVD
Reserved
OutErrorSts
A parity error occurred on an outbound read. This bit will
not get set unless PAR_EN is set in the EXP_TIMING_CS
for which the parity error has occurred.
Bit Reset
Value
0h
0h
0h
Bit Access
RO
RWC
RWC
OutErrorSts is generated to forms exp_parity_error which is routed to the Interrupt
Controller and can generate interrupts to the processor core. In the event of multiple
outbound parity errors, there is a race condition between when software performs a
write to clear the EXP_PARITY_STATUS register and setting the InErrorSts/OutErrorSts
error bit in hardware.
If the software clears the error bit before another parity error, the EXP_PARITY_STATUS
register will be set again. However if software clears the error bit on or after another
parity error, the EXP_PARITY_STATUS register will be cleared.
42.6
Performance Estimation
The bandwidth that can be supported on the expansion bus depends on the latencies
through the system and the nature of the protocol on the expansion bus. All latencies
are dependent on whether the transaction is read or write.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1703