EP80579 Datasheet, PDF (171/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Figure 6-5. Power Rail Sequence Timing (No Sustain Well Power Management)
SYS_PWROK GBE_AUX_PWR_GOOD
VRMPWRGD/ CPU_VRD_PWR_GD
Table 6-4. Power Rail Sequence Signal Timings
Sym
Parameter
Min
Max
Units
Notes
t200
VCCPRTC active to RTCRST# inactive
18
–
ms
t201
Suspend 5 V active to Suspend 3.3 V active
0
–
ms
1
t202
Suspend 3.3 V active to Suspend 2.5 V active
0
–
ms
2
t203
Suspend 2.5 V active to Suspend 1.2 V active
0
–
ms
3
t204
Suspend supplies active to RSMRST# inactive
10
–
ms
t205
VCCPRTC supply active to Suspend supplies active
0
–
ms
4
t209
Core 5 V active to Core 3.3 V active
0
–
ms
1
NOTES:
1. The 5 V supply must power up before its associated 3.3 V supply within 0.3 V, and must power down after the 3.3 V supply
within 0.3V.
2. Ensure the following: a) Suspend 3.3 V must power up before Suspend 2.5 V or after Suspend 2.5 within 0.3 V, b) Suspend
2.5 V must power down before Suspend 3.3 V or after Suspend 3.3 V within 0.3 V.
3. Ensure the following: a) Suspend 2.5 V must power up before Suspend 1.2 V or after Suspend 1.2 V within 0.3 V, b) Suspend
1.2 V must power down before Suspend 2.5 V or after Suspend 2.5 V within 0.3 V.
4. The VccSus supplies must never be active while the VCCPRTC supply is inactive.
5. Ensure the following a) Core 3.3 V must power up before Core 2.5 V or after Core 2.5 V within 0.3 V, b) Core 2.5 V must
power down before Core 3.3 V or after Core 3.3 V within 0.3 V.
6. Ensure the following: a) Core 2.5 V must power up before Vcc1.2 V or after Core 1.2 V within 0.3 V, b) Core 1.2 V must power
down before Core 2.5 V or after Core 2.5 V within 0.3 V.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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