EP80579 Datasheet, PDF (436/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-47. Offset 7Ch: DRC - DRAM Controller Mode Register (Sheet 2 of 2)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:0
Offset Start: 7Ch
Offset End: 7Fh
Size: 32 bit
Default: 00000002h
Power Well: Core
Bit Range
11 :10
99
78
06 :05
04 04
Bit Acronym
Bit Description
Sticky
DDR Chip select output disable
bit[11] = CS[1]
CSDIS
bit[10] = CS[0]
Y
0 = Enabled
1 = Disabled
Reserved Reserved
N
Reserved_2 Reserved_RW_Sticky
Y
DRAM ODT Disable: bit[5] = ODT[0]
ODTDIS
bit[6] = ODT[1]
0 = Enables the use of ODT when running
Y
1 = Disables (tristates) the use of ODT when running
CKE pin mode:
0 = Force low. Forces the state of CKE[1:0] low. When this
bit is cleared it over-rides all functionality that drives the
CKEPNM
CKE pin and forces it low. SW needs to set this bit for
normal operation
Y
1 = Enable CKE[1:0]. BIOS will set this bit to a 1 for
normal operating mode.
Bit Reset
Value
00b
0b
00b
00b
0b
Bit Access
RW
RO
RW
RW
RW
The PLL only supports one update of ratio (the lower nibble
of this register). This register defaults to DDR2-400
This field reflects BIOS selection of DDR speed, which may
have been “down-binned” due to fuse settings (see
SDRC.FUSESPEED)
3 :0
Encoding
DDR
Data
Speed
DDR
CMD
Freq
(MT/s)
(Mhz)
DS
0x10
400
200
Default
0x00
533
266
0111
667
333
0101
800
400
Others
Reserve
d
Y
0010b
RWO
Intel^® EP80579 Integrated Processor Product Line Datasheet
436
August 2009
Order Number: 320066-003US