EP80579 Datasheet, PDF (954/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 25-21. USBCMD: USB Command Register (Sheet 1 of 2)
Description:
View: PCI
BAR: USBIOBAR (IO)
Bus:Device:Function: 0:29:0
Offset Start: 00h
Offset End: 01h
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
15 : 09
08
07
06
05
04
Bit Acronym
Bit Description
Sticky
Reserved
Reserved
MAXP
CF
SWDBG
FGR
Reserved.
1 = Reserved
Max Packet:
0 = 32 bytes.
1 = 64 bytes.
This bit selects the maximum packet size that can be
used for full speed bandwidth reclamation at the end of
a frame. This value is used by the Host Controller to
determine whether it should initiate another transaction
based on the time remaining in the SOF counter. Use of
reclamation packets larger than the programmed size
will cause a Babble error if executed during the critical
window at frame end. The Babble error results in the
offending endpoint being stalled. Software is responsible
for ensuring that any packet which could be executed
under bandwidth reclamation be within this size limit.
Configure Flag:
0 = Indicates that software has not completed host
controller configuration.
1 = HCD software sets this bit as the last action in its
process of configuring the host controller.
This bit has no effect on the hardware. It is provided
only as a semaphore service for software.
Software Debug:
0 = Normal Mode.
1 = Debug mode. In software Debug mode, the Host
Controller clears the Run/Stop bit after the
completion of each USB transaction. The next
transaction is executed when software sets the
Run/Stop bit back to 1.
The SWDBG bit must only be manipulated when the
controller is in the stopped state. This can be
determined by checking the HCHalted bit in the USBSTS
register.
Force Global Resume:
0 = Software sets this bit to 0 after 20 ms has elapsed
to stop sending the Global Resume signal. At that
time all USB devices must be ready for bus activity.
1 = Host Controller sends the Global Resume signal on
the USB. The Host Controller sets this bit to 1 when
a resume event (connect, disconnect, or K-state) is
detected while in global suspend mode. The 1 to 0
transition causes the port to send a low speed EOP
signal. This bit will remain a 1 until the EOP has
completed.
Bit Reset
Value
0h
0h
0h
0h
0h
0h
Bit Access
RW
RW
RW
RW
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
954
August 2009
Order Number: 320066-003US