EP80579 Datasheet, PDF (443/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.1.1.48 Offset 90h: SPARECTL - SPARE Control Register
This register is used to set the prescale values for the leaky bucket error counting mechanism.
Table 16-52. Offset 90h: SPARECTL - SPARE Control Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:0
Offset Start: 90h
Offset End: 93h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 :24
23 :16
15 :12
Bit Acronym
Bit Description
Sticky
DEDEPV
SECEPV
DEDEPU
DED error prescale value: Prescale value ranges from 0-
255.
Y
SEC error prescale value: Prescale value ranges from 0-
255.
Y
DED error prescale unit:
0000
Never
0001
1 µs
0010
1 ms
0011
1s
0100
1 minute
Y
0101
1 hour
0110
1 day
0111
1 week
1XXX Never
Bit Reset
Value
00h
00h
0000b
Bit Access
RW
RW
RW
11 :08
SECEPU
SEC error prescale unit:
0000
Never
0001
1 µs
0010
1 ms
0011
1s
0100
1 minute
0101
1 hour
0110
1 day
0111
1 week
1XXX Never
Y
0000b
RW
07 :00
Reserved Reserved
N
00h
RO
16.1.1.49 Offset B0h: DDR2ODTC - DDR2 ODT Control Register
The DDR2ODTC controls the behavior of the ODT[1:0] output pins. The ODT pins
control the on-die termination on the DDR DRAM devices. (To control the ODT behavior
on the EP80579 please refer to Section 11.4.3, “On-Die Termination (ODTZ) on the
EP80579”.)
The DDR2ODTC control register provides separate fields to control the ODT pin
behavior for each of the four possible active cases: read to rank0, read to rank1, write
to rank0, and write to rank1. Each field is two bits wide as there are two ODT pins on
the EP80579. Please refer the different ODT configurations that the EP80579 supports
as shown in Figure 11-4, “ODT Timing on Back-to-Back Reads to Different Slots” on
page 300 and Figure 11-5, “ODT Timing on Back-to-Back Writes to Different Slots” on
page 301.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
443