EP80579 Datasheet, PDF (387/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
their endpoints, and the acknowledge “pushes” any pending inbound traffic all the way
to the root. This prevents “trapping” transactions or PME messages somewhere in the
hierarchy at the time power is dropped, ultimately causing them to be lost.
In a pure PCI Express design, the PME_TURN_OFF packet would originate directly at
the power manager, or perhaps at the IICH providing connection between the power
manager and the remainder of the core logic. Neither the power manager nor the IICH
is aware of the PCI Express messaging mechanism, thus the IMCH provides device-
specific control and status bits for use by its ACPI BIOS.
The sequence of events to place a PCI Express device in an unpowered state is as
follows:
1. PCI-PM or ACPI-compliant O/S software is called to place the system into a low-
power sleep state (S3, S4 or S5), prepares for suspension, and calls ACPI BIOS to
carry out the platform power transition.
2. The BIOS then communicates to the root complex that all PCI Express devices must
prepare for power-off. This is accomplished through the device-specific
configuration space of the internal virtual PCI-to-PCI bridges with subordinate PCI
Express hierarchies. The BIOS must configure each active root port to power-down.
When the configuration write is received to set the “PM Turn Off” bit, the associated
root port transmits a PM_Turn_Off message downstream. At this point, any traffic
in-flight continues to be handled normally by the IMCH – routed outbound, and
completed inbound.
3. The target PCI Express device ceases generation of new transactions inbound,
waits for all pending transactions to complete and prepares to lose power and
clocking. If the target device has a subordinate hierarchy of its own, it propagates
the PM_Turn_Off message downstream and waits for acknowledges from all
subordinate ports. Once ready to be brought off-line, the target device issues a
PM_TO_Ack TLP cycle in acknowledgement back to the root. Note that the link is
still communicative at this point, with both power and clock available.
4. After issuing the PM_TO_Ack cycle, the downstream device then issues a
PM_Enter_L23 DLLP continuously upstream until it receives an acknowledge. In
response to the PM_TO_Ack, the root port will commence the PCI Express
handshake sequence necessary to sets its “Turn Off Ack” status bit. In response to
the PM_Enter_L23 DLLP, the root transitions its downstream link to the electrical
idle state. (This protocol sequence directly mirrors the L1 entry sequence.)
5. ACPI BIOS, which has been waiting for all of the “Turn Off Ack” status bits to assert,
now clears all the command and status bits associated with the PME_TURN_OFF.
The routine then informs the power manager to go ahead with the change to the
system power state.
Note that software is required (by the PCI Express specification) to implement a
“dead-man” timer such that a failure to receive a full complement of “Turn Off Ack”
status bits does not result in an indefinite hang. This timeout is nominally 1 second,
after which the power state change proceeds regardless.
6. The power manager drops power and clocking to the target device(s), and all
associated links automatically transition to either the L2 or L3 uncommunicative
power states. The links enter L2 if Vaux is supplied by the platform, otherwise they
enter L3. (Note that the IMCH does not support Vaux, so all downstream lanes will
necessarily go to the L3 state.) The platform remains in the low-power state until a
wake event is signaled.
In a fully PCI Express aware core logic implementation, the ACPI BIOS would not need
to act as the interlock between the IMCH and the power manager, as all that
functionality would be handled in hardware via direct messaging.
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August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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