EP80579 Datasheet, PDF (911/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 24-20. Offset 02h: HCTL: Host Control Register (Sheet 4 of 4)
Description:
View: PCI
BAR: SM_BASE (IO)
Bus:Device:Function: 0:31:3
Offset Start: 02h
Offset End: 02h
Size: 8 bit
Default: 00h
Power Well: Resume
Bit Range Bit Acronym
Bit Description
Sticky
Bit Reset
Value
Bit Access
04 : 02
SMB_CMD
(cont’d)
Bits Name
Command Description
This command uses the transmit slave
address, command, DATA0 and the
Block Data Byte register. For block write,
the count is stored in the DATA0 register
and indicates how many bytes of data
will be transferred. For block read, the
count is received and stored in the
111
Block-
Process
DATA0 register. Bit 0 of the slave
address register always indicate a write
command. For writes, data is retrieved
from the first m (where m is equal to the
specified count) addresses of the SRAM
array. For reads, the data is stored in the
Block Data Byte register.
Note: E32B bit in the Auxiliary
Control Register must be set
for this command to work.
0h
RW
0 = Normal SMBus host controller functionality.
1 = Kills the current host transaction taking place, sets
01
KILL
the FAILED status bit, and asserts the interrupt (or
SMI#). This bit, once set, must be cleared by
software to allow the SMBus host controller to
function normally.
0 = Disable
00
INTREN 1 = Enable the generation of an interrupt or SMI# upon
the completion of the command
0h
RW
0h
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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