EP80579 Datasheet, PDF (303/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
11.4.6
RCOMP
The EP80579 supports RCOMP for the DDR pads. RCOMP control is implemented for 2
groups of DDR pads. The RCOMP used for the 2 groups can either be static or dynamic
based on DDRIOMC2.LEGOVERRIDE[5:4]. For more details on how to control the
RCOMP for the 2 groups of DDR pads please see Section 16.5.1.64, “Offset 268h:
DDRIOMC2 - DDR IO Mode Control Register 2”. The final values that are used for Group
1 and Group 2 drivers can be viewed using the bits in Section 16.5.1.29, “Offset F0h:
DIOMON - DDR I/O Monitor Register”.
• Group1: Data, data mask and data strobes:
— DDRIOMC2.LEGOVERRIDE[4:0] bits can be used in dynamic mode to achieve
the target impedance on the group 1 DDR pads. In dynamic RCOMP mode,
these CSR bits control several pull-up devices that are binary sized. The pull-up
devices are tuned using an external resistor (Rext). In Static mode,
DDRIOMC2.LEGOVERRIDE[3:0] determines the RCOMP value used by the
Group 1 DDRIO pads.
• Group2: Command, Address and Clock:
— In dynamic RCOMP mode the digital control for these group of DDR pads is
derived by multiplying the group 1 digital control by a factor determined by
DDRIOMC2.LEGOVERRIDE[6:9]. In static RCOMP mode,
DDRIOMC2.LEGOVERRIDE[6:9] directly controls the RCOMP value used by the
Group 2 DDRIO pads.
11.4.7
DDR2 MR and EMR settings
Table 11-16 shows the supported settings of DDR2 mode register (MR) and extended
mode register (EMR). Note that only the architecturally relevant settings of the MR and
EMR are listed in this table. These registers can be updated using the MRS and EMRS
commands. Please see Section 16.5.1.3, “Offset 40h: DCALCSR – DDR Calibration
Control and Status Register” and Section 16.5.1.4, “Offset 44h: DCALADDR - DDR
Calibration Address Register” for more details on generation of MRS and EMRS
commands.
Table 11-16. Supported DDR2 MR and EMR settings
MR/EMR Feature
Burst Type
Burst Length
Write Recovery for Auto-precharge
CAS Latency
ODT (EMR)
OCD Calibration (EMR)
Additive Latency (EMR)
EP80579 Support
Sequential only
4 (64-bit mode) and 8 (32-bit mode)
Supported. Settings based on speed bins. Please see Section
16.0, “IMCH Registers” for details.
3, 4, 5 and 6 depending upon Speed bin. Please see Table 11-12
and Section 16.0, “IMCH Registers” for more details.
Supported.
Please see Section 11.4.2 for more details.
Not Supported.
Not Supported.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
303