EP80579 Datasheet, PDF (1738/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 48-6. Sideband Miscellaneous Signals (Sheet 2 of 2)
Signal Name
IO Type
STPCLK_OUT#
LVTTL,3.3V
RCIN#
LVTTL,3.3V
A20GATE
LVTTL,3.3V
CPURST#
LVTTL,3.3V
CPUPWRGD_OUT LVTTL,3.3V
IERR#
LVTTL,3.3V
TOTAL
Direction
Ball
Count
External
Pull-Up/
Down
[Ohms]
BSC/
XOR
Signal Description Normal/Alternate Mode
O
1
I
1
BSC
BSC
Stop Clock Request: This EP80579 output signal
is made visible to the platform for debug
purposes only. This internal EP80579 signal is an
active-low output synchronous to PCICLK that is
asserted in response to one of many hardware
or software events. When the processor samples
STPCLK_OUT# asserted, it causes the processor
to enter a low power Stop-Grant state. The
processor issues a Stop-Grant Acknowledge
transaction, and stops providing internal clock
signals to all processor core units except the
CPU FSB and CPU APIC units. The processor
continues to snoop bus transactions and service
interrupts while in Stop-Grant state. When
STPCLK_OUT# is deasserted, the processor
restarts its internal clock to all units and
resumes execution. The assertion of
STPCLK_OUT# has no effect on the bus clock;
STPCLK_OUT# is an asynchronous CPU input
generated by the EP80579 IICH.
Keyboard Controller Reset Processor: The
keyboard controller can generate INIT_N to the
processor. This saves the external OR gate of
other sources of INIT_N. When the EP80579
detects the assertion of this signal, INIT_N is
generated for 16 PCICLK clocks.
I
1
O
1
BSC
BSC
The EP80579 will ignore RCIN# assertion during
transitions to the S3, S4 and S5 states.
A20 Gate: A signal from the keyboard controller.
Acts as an alternative method to force the
A20M_N signal active. Saves the external OR
gate needed with various other chipsets.
Processor Bus Reset: The IMCH asserts
CPURST# while RSTIN# is asserted and for
approximately 1 ms after RSTIN# is deasserted.
The CPURST# allows the processors to begin
execution in a known state.
This EP80579 signal is for the use by the debug
tool purpose.
OD O
1
10K Up
BSC
CPUPWRGD is an open drain signal, this signal
requires an external pull-up resistor. This
EP80579 output signal is made externally visible
to the platform for debug purposes only.
CPUPWRGD monitors an internal EP80579 signal
connected directly from the IICH to the
processor and represents a logical AND of
PWROK and VRMPWRGD signals. This signal also
must be driven high throughout Boundary Scan
operation.
O
1
BSC
IERR (Internal Error) is asserted by a processor
as the result of an internal error. Assertion of
IERR is usually accompanied by a SHUTDOWN
transaction on the FSB. This transaction may
optionally be converted to an external error
signal (e.g., NMI) by the EP80579. The
processor will keep IERR asserted until the
assertion of INIT33V_OUT# or the EP80579 is
reset using SYS_RESET#. For termination
requirements please refer to the platform design
guides.
10
Intel^® EP80579 Integrated Processor Product Line Datasheet
1738
August 2009
Order Number: 320066-003US