EP80579 Datasheet, PDF (1167/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
32.3.7
If a timer has been configured to level-triggered mode, then its interrupt must be
cleared by the software. This is done by reading the interrupt status register and
writing a one back to the bit position for the interrupt to be cleared.
Independent of the mode, software can read the value in the main counter to see how
time has passed between when the interrupt was generated and when it was first
serviced.
If a timer 0 is set up to generate a periodic interrupt, the software can check to see
how much time remains until the next interrupt by checking the timer value register.
Unloading Device Driver Issues
When unloading device drivers for the HPET High Precision Event Timer, some
precautions may be needed. For example, if the legacy routing is used, when the HPET
High Precision Event Timer is disabled, a spurious interrupt could occur. The OS must
mask interrupts prior to clearing the LEG_RT_CNF bit.
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August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1167