EP80579 Datasheet, PDF (412/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-28. Offset 9Eh: SMRAM - System Management RAM Control Register (Sheet 2 of
2)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:0
Offset Start: 9Eh
Offset End: 9Eh
Size: 8 bit
Default: 02h
Power Well: Core
Bit Range
05
04
03
02 : 00
Bit Acronym
Bit Description
Sticky
D_CLS
SMM Space Closed:
0 = SMM space DRAM is accessible to data references
1 = SMM space DRAM is not accessible to data references,
even if SMM decode is active. Code references may
still access SMM space DRAM. This allows SMM
software to reference through SMM space to update
the display even when SMM is mapped over the VGA
range.
Software must ensure that D_OPEN=1 and D_CLS=1 are
not set at the same time.
Note: The D_CLS bit only applies to Compatible SMM
space.
D_LCK
SMM Space Locked:
0 = SMM space unlocked
1 = And then D_OPEN is reset to 0 and D_LCK, D_OPEN,
H_SMRAME, TSEG_SZ and T_EN become Read-Only.
D_LCK can be set to 1 via a normal configuration
space write but can only be cleared by a Full Reset.
The combination of D_LCK and D_OPEN provide
convenience with security.
The BIOS can use the D_OPEN function to initialize SMM
space and then use D_LCK to lock SMM space in the future
so that no application software (or BIOS itself) can violate
the integrity of SMM space, even if the program has
knowledge of the D_OPEN function.
Reserved Reserved.
C_BASE_SEG
Compatible SMM Space Base Segment: This field
indicates the location of SMM space. SMM DRAM is not
remapped. It is simply made visible if the conditions are
right to access SMM space, otherwise the access is treated
as a VGA access. Since the IMCH supports only the SMM
space between A0000 and BFFFF, this field is hardwired to
010.
Bit Reset
Value
0b
0b
0b
010b
Bit Access
RW
RWS
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
412
August 2009
Order Number: 320066-003US