EP80579 Datasheet, PDF (586/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-211.Offset 140h: PEAUNITERR - PCI Express Unit Error Register (Sheet 1 of 2)
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 140h
Offset End: 143h
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 140h
Offset End: 143h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 : 16
15
14
13
12
Bit Acronym
Bit Description
Sticky
Reserved Reserved for future additions.
UPQOS
Upstream Posted Queue Overflow Status: This bit is
one of the components of the Receiver Overflow Status bit
in the UNCERRSTS register. Even though this bit can be
set, it is only reported through the receiver overflow bit in
the UNCERRSTS register. The setting of this bit is never
logged in the local FERR/NERR registers or subsequently
the global FERR/NERR registers, nor does it cause a SCI/
SMI/SERR or MCERR message. At most, when the report
Y
mask, is disabled, it could affect the unit error pointer. This
functionality is provided as an aid to debug.
0 = Software clears this bit by writing a ‘1’ to the bit
position.
1 = Overflow occurred for one of the posted header or
data queues.
Upstream Non-Posted Queue Overflow Status: This
bit is set if an overflow occurs for the non-posted header
queue. There is no upstream non-posted data queue. It is
one of the components of the Receiver Overflow Status bit
in the UNCERRSTS register. Even though this bit can be
set, it is only reported through the receiver overflow bit in
the UNCERRSTS register. The setting of this bit is never
UNPQOS ^{logged in the local FERR/NERR registers or subsequently}
Y
the global FERR/NERR registers, nor is it a cause for a SCI/
SMI/SERR or MCERR message. At most, when the report
mask, is disabled, it could affect the unit error pointer. This
functionality is provided as an aid to debug.
0 = Software clears this bit by writing a ‘1’ to the bit
position.
1 = Overflow occurred for the non-posted header queues.
Upstream Completion Queue Overflow Status
[STICKY]: This bit is set if an overflow occurs for either
the completion header or data queues It is one of the
components of the Receiver Overflow Status bit in the
UNCERRSTS register. Even though this bit can be set, it is
only reported through the receiver overflow bit in the
UNCERRSTS register. The setting of this bit is never logged
UCQOS
in the local FERR/NERR registers or subsequently the
global FERR/NERR registers, nor is it a cause a SCI/SMI/
Y
SERR or MCERR message. This functionality is provided as
an aid to debug.
0 = Software clears this bit by writing a ‘1’ to the bit
position.
1 = Overflow occurred for one of the completion header or
data queues.
0 = LLE Protocol Error [STICKY]: This bit is set when
the transaction layer detects a protocol error on the
receiver interface from the LLE. Such an event should
cause retraining eventually, but not necessarily
LPE
immediately. The transaction with a problem is
Y
dropped. Software clears this bit by writing a ‘1’ to the
bit position.
1 = Transaction layer detected a protocol error on the
receiver interface from the LLE
Bit Reset
Value
0000h
0b
0b
0b
0b
Bit Access
RWC
RWC
RWC
RWC
Intel^® EP80579 Integrated Processor Product Line Datasheet
586
August 2009
Order Number: 320066-003US