EP80579 Datasheet, PDF (849/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
23.2.1.2 Offset 02h: PSTS – Primary Status Register
Table 23-45. Offset 02h: PSTS – Primary Status Register
Description:
View: PCI
Base Address: LBAR (IO)
Bus:Device:Function: 0:31:2
Offset Start: 02h
Offset End: 02h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07
06
05
04 : 03
02
01
00
Bit Acronym
Bit Description
Sticky
PRDIS
D1DC
D0DC
Reserved
I
ERR
ACT
PRD Interrupt Status (PRDIS): This bit is set when
the host controller completes execution of a PRD that
has its PRD_INT bit set.
Device 1 DMA Capable (D1DC): A scratchpad bit set
SW to indicate that device 1 of this channel is capable of
DMA transfers. This bit has no effect on the hardware.
Device 0 DMA Capable (D0DC): A scratchpad bit set
by SW to indicate that device 0 of this channel is
capable of DMA transfers. This bit has no effect on the
hardware.
Reserved
Interrupt (I): This bit is set when a device FIS is
received with the ‘I’ bit has been set provided that
software has not disabled interrupt via the nIEN bit of
Device Control Register.
Error (ERR): This bit is set when the controller
encounters an error during the transfer and must stop
the transfer. See section 1.5.2 for the list of errors that
set this bit
Active (ACT): Set by the host when the START bit is
written to the Command register, and cleared by the
host when the last transfer for a region is performed,
where EOT for that region is set in the region descriptor,
and when the START bit is cleared in the Command
register and the controller has returned to an idle
condition.
Bit Reset
Value
0h
0h
0h
0h
0h
0h
0h
Bit Access
RWC
RW
RW
RO
RWC
RWC
RO
23.2.1.3 Offset 04h: PDTP – Primary Descriptor Table Pointer Register
Table 23-46. Offset 04h: PDTP – Primary Descriptor Table Pointer Register
Description:
View: PCI
Base Address: LBAR (IO)
Bus:Device:Function: 0:31:2
Offset Start: 04h
Offset End: 07h
Size: 32 bit
Default: Variable
Power Well: Core
Bit Range
31 : 02
01 : 00
Bit Acronym
Bit Description
Sticky
DBA
Reserved
Descriptor Base Address (DBA): Corresponds to
A[31:2]. This table must not cross a 64K boundary in
memory. When read, the current value of the pointer is
returned
Reserved
Bit Reset
Value
X
00h
Bit Access
RW
RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
849