EP80579 Datasheet, PDF (188/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
This table illustrates how the global information can be tied to a particular register in
multiple register cases. In this table, the first and second instances of EG_MULT_DIFF
are in the “Core” and “Reset” power wells, respectively. Typically, this notation is only
be used for the power well.
It is also possible to incorporate the instance number in the name as Table 7-2
describes. Using the name EG_MULTI{2:1}_DIFF in Table 7-5 would identify two
physical registers with different names. The first, EG_MULTI2_DIFF, materializes
according to the PCI 2 and IA F 2 views, while the second, EG_MULTI1_DIFF,
materializes according to the PCI 1 and IA F 1 views.
Table 7-6 presents an example definition for the register EG_MULTI_SAME which
corresponds to two physical registers that materialize in the same “device”. The
instance EG_MULT_SAME[1] materializes at offset ACE0h in the I/O region defined by
BLAHBAR of PCI device 16 and at the fixed offset 100h in IA I/O space. The instance
EG_MULT_SAME[2] materializes at offset ACE4h in the I/O region defined by BLAHBAR
of PCI device 16 and at the fixed offset 120h in IA I/O space.
Table 7-6. EG_MULTI_SAME[1-2]: Example Multiple Registers in Same Device with
Different Views
Description: A set of two physical registers that materialize in the same device.
View: PCI
BAR: BLAHBAR (IO)
Bus:Device:Function: 0:16:0
Offset Start: ACE0h at 4h
Offset End: ACE3h at 4h
View: IA F Base Address: 0000h (IO)
Offset Start: 100h, 120h
Offset End: 103h, 123h
Size: 32 bit
Default: DEAD8086h
Power Well: Core
Bit Range
31 : 00
Bit Acronym
Bit Description
Sticky
Bit Reset
Value
Bit Access
BRMAGIC Blacker Magic Stuff: This field contains a magic number.
DEAD8086h
RO
Note that in this example, the strides do not need to be the same across the different
views.
Finally, Table 7-7 presents an example definition for the register EG_INDEX which
corresponds to a physical registers that materialize indirectly. To access the EG_INDEX
register, the starting offset 0100h (in double words of 32-bits) is written to the
APIC_IDX index register to select EG_INDEX which is then accessed through the
APIC_WND window registers.
Table 7-7. EG_INDEX: Example Single Indexed Register
Description: A single indexed register.
View: IA I
Win:Idx APIC_WND:APIC_IDX
Size: 32 bit
Default: 0ACEFACEh
Bit Range Bit Acronym
Bit Description
31 : 00
MAGIC
Magic Stuff: This field contains a magic number.
Offset Start: 0100h (4B)
Offset End: 0100h (4B)
Power Well: Core
Sticky
Bit Reset
Value
Bit Access
0ACEFACEh
RO
The offsets should always fit within the index register.
Intel^® EP80579 Integrated Processor Product Line Datasheet
188
August 2009
Order Number: 320066-003US