EP80579 Datasheet, PDF (521/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.4
Note:
Note:
PCI Express* Port A Standard and Enhanced Registers:
Bus 0, Devices 2 and 3, Function 0
Bus 0, Device 2, Function 0 is the PCI Express* Port A (in x8 mode) or port A0 (in x4
mode) virtual PCI-to-PCI bridge. The registers described here include both the standard
configuration space and the enhanced configuration space (starting at offset 100h).
Device 3 is the PCI Express* Port A1 virtual PCI-to-PCI bridge. Device 2 is PCI Express*
Port A (in x8 mode) or A0 (in x4 mode). Port A1’s associated PCI Express* link has a
maximum lane width of x4. When Device 2 is configured as a x8 PCI Express* link,
device 3 is not available. The registers described here include both the standard
configuration space and the enhanced configuration space (starting at offset 100h).
Except for the registers listed below, all registers for Device 3 are exactly the same as
for Device 2.
All registers are located in the Core power well.
For platforms not using PCIe should also disable PCI Express* logic per Section 9.2.1.1,
“Low power SKU with PCI Express ports removed”
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
521