EP80579 Datasheet, PDF (982/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 26-6. Offset 06h: DSR - Device Status Register (Sheet 2 of 2)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:29:7
Offset Start: 06h
Offset End: 07h
Size: 16 bit
Default: 0290h
Power Well: Core
Bit Range
13
12
11
10 :09
08
07
06
05
04
03
02 :00
Bit Acronym
Bit Description
Sticky
RMA
RTA
STA
DEVT
DPD
FB2BC
Reserved
C66
CLIST
IS
Reserved
Received Master-Abort Status:
0 = No master abort received by EHC on a memory
access.
1 = This bit is set when USB 2.0, as a master, receives a
master-abort status on a memory access. This is
treated as a Host Error and halts the DMA engines.
This event can optionally generate an SERR# by
setting the SERR# Enable bit and the SERR on Aborts
Enable (bit 3, offset 84h).
Software clears this bit by writing a ‘1’ to this bit location.
Received Target Abort Status:
0 = No target abort received by EHC on memory access.
1 = This bit is set when USB 2.0, as a master, receives a
target abort status on a memory access. This is
treated as a Host Error and halts the DMA engines.
This event can optionally generate an SERR# by
setting the SERR# Enable bit and the SERR on Aborts
Enable (bit 3, offset 84h).
Software clears this bit by writing a ‘1’ to this bit location.
Signaled Target-Abort Status: This bit is used to
indicate when the USB 2.0 function responds to a cycle
with a target abort. This should never occur, so this bit is
hard-wired to ‘0’.
DEVSEL# Timing Status: This 2-bit field defines the
timing for DEVSEL# assertion.
Master Data Parity Error Detected:
0 = No data parity error detected on USB 2.0 read
completion packet.
1 = This bit is set whenever a data parity error is
detected on a USBe read completion packet on the
internal interface to the USBe host controller and bit
6 of the Command register is set to 1.
Software clears this bit by writing a ‘1’ to this bit location.
Fast Back-to-Back Capable: Reserved as ‘1’.
User Definable Features: Reserved as ‘0’.
66 MHz Capable: Reserved as ‘0’.
Capabilities List: Hardwired to ‘1’ indicating that offset
34h contains a valid capabilities pointer.
Interrupt Status: This read-only bit reflects the state of
this function’s interrupt at the input of the enable/disable
logic.
0 = This bit will be 0 when the interrupt is deasserted.
1 = This bit is a 1 when the interrupt is asserted.
The value reported in this bit is independent of the value
in the Interrupt Enable bit.
This bit is added as part of the PCI 2.3 Specification.
Reserved.
Bit Reset
Value
0h
0h
0h
01h
0h
1
0h
0h
1
0h
000h
Bit Access
RWC
RWC
RO
RO
RWC
RO
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
982
August 2009
Order Number: 320066-003US