EP80579 Datasheet, PDF (1445/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 37-28. CTRL_AUX: Auxiliary Device Control Register (Sheet 2 of 2)
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 00E0h
Offset End: 00E3h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 00E0h
Offset End: 00E3h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 00E0h
Offset End: 00E3h
Size: 32 bits
Default: 00000100h
GbE0: Aux
Power Well: Gbe1/2:
Core
Bit Range
09 : 08
07 : 01
00
Bit Acronym
Bit Description
Sticky
ENDIANESS
Endianness:
These bits control the endianness of the data in memory.
These settings apply to all internal bus transactions,
including packet data and descriptors
‘00’ - LW Little--Endian, Byte Big-Endian
‘01’ - LW Little-Endian, Byte Little-Endian (default)
‘10’ - LW Big-Endian, Byte Big-Endian
‘11’ - LW Big-Endian, Byte Little-Endian
Refer to Section 37.5.14, “Endianness” for further details.
RSVD
Reserved
RGMII_RMII
RGMII/RMII Translation Gasket Select
• ‘0’ - RGMII
• ‘1’ - RMII
Bit Reset
Value
01h
0h
0h
Bit Access
RW
RO
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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