EP80579 Datasheet, PDF (478/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.2.1.31 Offset 7Ah: BUF_SMICMD - Memory Buffer SMI Command Register
This register enables various errors to generate an SMI NSI special cycle. When an
error flag is set in the FERR or NERR registers, it generates an SMI NSI special cycle
when enabled in the SMICMD register. Note that one and only one message type can be
enabled.
Table 16-85. Offset 7Ah: BUF_SMICMD - Memory Buffer SMI Command Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:1
Offset Start: 7Ah
Offset End: 7Ah
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range Bit Acronym
Bit Description
Sticky
07 : 04
03
02
01
00
Reserved Reserved
DPMWB_SMI
Internal DRAM Interface to PMWB Parity Error SMI
Enable: Generate SMI when parity error detected for
DRAM interface to PMWB when this bit is set.
0 = Disable
1 = Enable
Internal System Bus or I/O to PMWB Parity Error
SMI Enable: Generate SMI when parity error detected for
IOPMWB_SMI ^{internal System Bus or I/O to PMWB when this bit is set.}
0 = Disable
1 = Enable
Internal PMWB to System Bus Parity Error SMI
Enable: Generate SMI when parity error detected for
PMWBSYS_SMI ^{PMWB to System Bus when this bit is set.}
0 = Disable
1 = Enable
PMWBD_SMI
Internal PMWB to DRAM I/F Parity Error SMI Enable:
Generate SMI when parity error detected for PMWB to
DRAM I/F when this bit is set.
0 = Disable
1 = Enable
Bit Reset
Value
0h
0b
0b
0b
0b
Bit Access
RW
RW
RW
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
478
August 2009
Order Number: 320066-003US