EP80579 Datasheet, PDF (1176/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 33-10. Internal Register Descriptions
UART Register
Addresses
(Base + offset)
Base
Base
Base + 01H
Base + 02H
Base + 02H
Base + 03H
Base + 04H
Base + 05H
Base + 06H
Base + 07H
Base
Base + 01H
DLAB Bit
Value
0
0
0
X
X
X
X
X
X
X
1
1
Register Accessed
Receive BUFFER (Read-Only)
Transmit BUFFER (Write-Only)
Interrupt Enable (Read/Write)
Interrupt I.D. (Read-Only)
FIFO Control (Write-Only)
Line Control (Read/Write)
Modem Control (Read/Write)
Line Status (Read-Only)
Modem Status (Read-Only)
Scratch Pad (Read/Write)
Divisor Latch (Lower Byte, Read/Write)
Divisor Latch (Upper Byte, Read/Write)
Note:
Base Address for the UART registers listed in Table 33-10 is configurable. See Section
33.8.3, “SIW Configuration Register Summary” on page 1207 for details.
33.5.3.1
Offset 00h: RBR - Receive Buffer Register
In non-FIFO mode, this register holds the character received by the UART's Receive
Shift Register. If fewer than eight bits are received, the bits are right-justified and the
leading bits are zeroed. Reading the register empties the register and resets the Data
Ready (DR) bit in the Line Status Register to zero. Other (error) bits in the Line Status
Register are not cleared. In FIFO mode, this register latches the value of the data byte
at the top of the FIFO.
Table 33-11. Offset 00h: RBR - Receive Buffer Register
Description:
View: IA F
Base Address: Base (IO) (DLAB = 0)
Offset Start: 00h
Offset End: 00h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07 :00
Bit Acronym
Bit Description
Sticky
RB_7_0 Data byte received (bits [7:0]), least significant bit first
Bit Reset
Value
00h
Bit Access
RO
33.5.3.2
Offset 00h: THR - Transmit Holding Register
This register holds the next data byte to be transmitted. When the Transmit Shift
Register becomes empty, the contents of the Transmit Holding Register are loaded into
the shift register and the transmit data request (TDRQ) bit in the Line Status Register is
set to one.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1176
August 2009
Order Number: 320066-003US