EP80579 Datasheet, PDF (408/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Note:
Note:
“RWO or RO” bits:
All of the “RWO or RO” bits in this register are gated with a SKU value. The SKU value
has priority over values written by software. This means that if the SKU value of this bit
is set to a 0, neither a configuration write or a reset sets this bit.
If a SKU value is not present then the register will have RO access.
When a SKU value is not present, the device is invisible to software. Writes to this
register when the SKU value is not present, will have no effect, always returning ‘0’
when read.
If a SKU value is present the register will have RWO access.
BIOS must write a bit to a 0 to disable a device, or a 1 to enable a device. This register
can only be written once. After the first write, the register is locked.
RWO Devices that are disabled via software can only be re-enabled via a reset. This
register should only be written to at boot time when there is no traffic to or from the
PEA.
Once software or BIOS has written these RWO register bits for the first time after
power-up, the register value locks, and cannot be further updated.
In other words, once software has disabled RWO devices, they can only be re-enabled
via a reset. For RWO access bits the IMCH does not support turning off a device, and
then turning it back on. (The reverse is also true: once software has enabled RWO
devices, they can only be re-disabled via a reset.)
RW bits:
Two devices have RW bit access. These devices need to be enabled/disabled for power
management during normal operation
Table 16-26. Offset 9Ch: DEVPRES - Device Present Register (Sheet 1 of 2)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:0
Offset Start: 9Ch
Offset End: 9Ch
Size: 8 bit
Default: 33h
Bit Range Bit Acronym
Bit Description
07 : 06
05
04
Reserved Reserved
Reserved Reserved
0 = PCI-to-PCI Bridge is disabled.
Device_4_Prese
nt
1
=
PCI-to-PCI Bridge is enabled.
Power Well: Core
Sticky
Bit Reset
Value
0b
1b
Bit Access
RW
1b
RW
0 = PCI Express* port A1 (x4) is disabled. In this state,
port A (Device 2) can operate with a maximum x8 link
03
Device_3_Prese
width.
nt
1 = PCI Express port A1 is enabled. In this state, port A
can operate with a maximum x4 link width.When the SKU
value is cleared, this field is read/write. When the SKU
value is set, this field becomes a read-only ‘0’
0b
RWO or RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
408
August 2009
Order Number: 320066-003US