EP80579 Datasheet, PDF (710/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 17-29. Offset 3418h: FD - Function Disable Register (Sheet 2 of 2)
Description:
View: PCI
BAR: RCBA
Bus:Device:Function: 0:31:0
Offset Start: 3418h
Offset End: 341Bh
Size: 32 bit
Default: 00000080h
Power Well: Core
Bit Range
14
13 : 12
11
10
09
08
07
06
05
04
03
02
01
00
Bit Acronym
Bit Description
Sticky
LBD
Reserved
Reserved
Reserved
Reserved
U1D
Reserved
Reserved
Reserved
Reserved
SD
SAD
Reserved
Reserved
LPC Bridge Disable:
0 = The LPC bridge is enabled.
1 = The LPC bridge is disabled. Unlike the other disables
in this register, the following additional spaces no
longer are decoded by the LPC bridge:
• Memory cycles below 16 MBytes (1000000h)
• I/O cycles below 64 Kbytes (10000h)
• The Internal I/OxAPIC at FEC0_0000 to FECF_FFFF
• Memory cycles in the LPC BIOS range below 4 GByte
are still decoded when this bit is set, but the aliases at
the top of 1 MByte (the E and F segment) are no
longer decoded.
Reserved
Reserved
Reserved
Reserved
USB1 #1 Disable:
0 = When reset, the first USB 1.1 controller (ports 0 and
1) is enabled.
1 = When set, the first USB 1.1 controller (ports 0 and 1)
is disabled.
Reserved
Reserved
Reserved
Reserved
SM Bus Disable:
0 = The SM Bus controller is enabled.
1 = The SM Bus controller is disabled.
Serial ATA Disable:
0 = The serial ATA controller is enabled.
1 = The serial ATA controller is disabled
Reserved
Reserved
Bit Reset
Value
0h
0h
0h
0h
0h
0h
1h
0h
0h
0h
0h
0h
0h
Bit Access
RW
RO
RO
RO
RO
RW
RO
RO
RO
RO
RW
RW
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
710
August 2009
Order Number: 320066-003US