EP80579 Datasheet, PDF (1493/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.6.5.2
TIPG – Transmit IPG Register
This register controls the Inter Packet Gap (IPG) timer.
Table 37-68. TIPG: Transmit IPG Register (Sheet 1 of 2)
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 0410h
Offset End: 0413h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 0410h
Offset End: 0413h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 0410h
Offset End: 0413h
Size: 32 bits
Default: 00602008h
GbE0: Aux
Power Well: Gbe1/2:
Core
Bit Range
31 : 30
29 : 20
Bit Acronym
Bit Description
Sticky
Rsvd
IPGR2
Reserved
IPG Receive Time 2.
Specifies the total length of the IPG time for non back-to-
back transmissions. Measured in increments of the MAC
clock:
• 8 ns MAC clock when operating @ 1 Gbps (82544GC/EI
only).
• 80 ns MAC clock when operating @ 100 Mbps
• 800 ns MAC clock when operating @ 10 Mbps.
In order to calculate the actual IPG value, a value of six
should be added to the IPGR2 value as six MAC clocks are
used by the MAC for synchronization and internal engines.
For the IEEE 802.3 standard IPG value of 96-bit time, the
value that should be programmed into IPGR2 is six (total
IPG delay of 12 MAC clock cycles)
According to the IEEE802.3 standard, IPGR1 should be 2/3
of IPGR2 value.IPGR2 is significant only in half-duplex
mode of operation.
Bit Reset
Value
0h
0x6h
Bit Access
RV
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1493