EP80579 Datasheet, PDF (88/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Revision History
Revision History
Date
August
2009
Revision Description
Changed the following signal names:
• EX_REQ_GNT# to Reserved 19
• EX_SLAVE_CS# to Reserved 20
• EX_GNT_REQ# to NC57
• EX_WAIT# to NC58
• EX_WDTXFER to NC59
Corrected signal name:
• SIU_CST1 to SIU_CST1#
• SIU_CST2 to SIU_CST2#
Updated:
• Section Product Features
• Table 1-4, “Glossary Table”
• Table 2-1, “EP80579 External Interface Summary”
• Table 5-32, “Summary of Local Expansion Bus Error Conditions”
• Table 6-5, “Powergood Reset Timings”
• Section 6.3.2.1, “Transitioning Between Power States”
• Section 11.4.6, “RCOMP”
003
• Section 16.5.1.64, “Offset 268h: DDRIOMC2 - DDR IO Mode Control Register 2”
• Section 23.1.1.5, “PI - Programming Interface Register”
• Section 37.5.11.6.3, “Checksum Word Calculation”
• Section 42.5, “Register Summary”
• Table 42-7, “EXP_TIMING_CS[1-7] - Expansion Bus Timing Registers”
• Table 42-9, “EXP_PARITY_STATUS - Expansion Bus Parity Status Register”
• Table 42-10, “LEB Performance Calculation - Estimated AIOC Latencies”
• Table 48-24, “Expansion Bus Signals”
• Table 48-22, “Gigabit Ethernet Interface Signals” with signal name changes
• Figure 49-28, “LPC Valid Delay from Rising Clock Edge Diagram” and Figure 49-32, “IICH Clock
(CLK14) Timing Diagram” with signal name corrections
• Table 49-10, “Power Management DC Input Characteristics” PWRBTN# pin
• Table 49-11, “Power Management DC Output Characteristics” PWRBTN# pin
• Table 49-36, “SMBus DC Input Characteristics” Intruder# pin
• Table 49-37, “SMBus DC Output Characteristics” Intruder# pin
• Table 49-106, “IMCH Reset Signals DC Input Characteristics” CLK100
(Continued Next Page)
Intel^® EP80579 Integrated Processor Product Line Datasheet
88
August 2009
Order Number: 320066-003US