EP80579 Datasheet, PDF (1553/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Figure 37-52.Reset Deasserted after before EEPROM Read Completes
power
tppg
1
PWR_OK
CLK
trpg
RESET
Reading EEPROM
tpgee
5 _tpgprst
2
tee
Read EEPROM
tprmem 10 _{Memory Access Enable 11}
Wakeup Enabled
4
APM
DState
Dr
D0u
D0a
Note
1
2
4
5
10
11
PWR_OK must not be asserted until all power supplies are good
An EEPROM read is started on the rising edge of PWR_OK and RESET.
APM Wakeups may be enabled based on what is read from the EEPROM.
The system can delay an arbitrary time before deasserting RESET.
The system can delay an arbitrary time before enabling Memory Access.
Writing a 1 to the Memory Access Enable bit in the PCI Command Register will transition the
MAC from D0u to D0 state
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1553