EP80579 Datasheet, PDF (1185/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 33-19. Offset 04h: MCR - Modem Control Register (Sheet 2 of 2)
Description:
View: IA F
Base Address: Base (IO)
Offset Start: 04h
Offset End: 04h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
02
01
00
Bit Acronym
Bit Description
Sticky
OUT1
RTS
DTR
Test bit: This bit is used only in Loopback test mode.
See (LOOP) Above.
Request to Send: This bit controls the Request to Send
(RTS#) output pin. Bit 1 affects the RTS# output in a
manner identical to that described below for the DTR
bit.
0 = RTS# pin is 1
1 = RTS# pin is 0
Data Terminal Ready: This bit controls the Data
Terminal Ready output. When bit 0 is set to a logic 1,
the DTR# output is force to a logic 0. When bit 0 is reset
to a logic 0, the DTR# output pin is forced to a logic 1.
• The DTR# output of the UART may be applied to an
EIA inverting line driver (such as the DS1488) to
obtain the proper polarity input at the succeeding
modem or data set.
0 = DTR# pin is 1
1 = DTR# pin is 0
Bit Reset
Value
0b
0b
0b
Bit Access
RW
RW
RW
33.5.3.8
Offset 05h: LSR - Line Status Register
This register provides status information to the processor concerning the data
transfers. Bits 5 and 6 show information about the transmitter section. The rest of the
bits contain information about the receiver.
In non-FIFO mode, three of the LSR register bits, parity error, framing error, and break
interrupt, show the error status of the character that has just been received. In FIFO
mode, these three bits of status are stored with each received character in the FIFO.
LSR shows the status bits of the character at the top of the FIFO. When the character at
the top of the FIFO has errors, the LSR error bits are set and are not cleared until
software reads LSR, even if the character in the FIFO is read and a new character is
now at the top of the FIFO.
Bits one through four are the error conditions that produce a receiver line status
interrupt when any of the corresponding conditions are detected and the interrupt is
enabled. These bits are not cleared by reading the erroneous byte from the FIFO or
receive buffer. They are cleared only by reading LSR. In FIFO mode, the line status
interrupt occurs only when the erroneous byte is at the top of the FIFO. If the
erroneous byte being received is not at the top of the FIFO, an interrupt is generated
only after the previous bytes are read and the erroneous byte is moved to the top of
the FIFO.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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