EP80579 Datasheet, PDF (878/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 23-75. Errors during unknown FIS type³ reception
Error Type
Unknown FIS Type
Host Controller Behavior
The unknown FIS type is itself an error
condition, and will result in bus master error
bits being set and R_ERR being returned.
Table 23-76. Errors during FIS transmission
Error Type
Host Controller Behavior
Non-data FIS: Received R_ERR (includes link protocol errors
during transmission), or phyrdy dropping unexpectedly
Retry the FIS.
Data FIS: Received R_ERR (includes link protocol errors
during transmission), or phyrdy dropping unexpectedly
Set the bus master error bit. Do not retry the
FIS.
Notes:
1.
Malformed FIS = FIS not constructed according to link layer protocols
2.
Illegal length for corresponding FIS type; For example the following FIS types and their
corresponding lengths:
D2H Dma_Activate FIS length = 1DW
D2H Register FIS = 5 DW
D2H Pio_Setup FIS = 5DW
D2H Set-Device-Bits = 2DW
D2H Bist FIS = 3DW
3.
Zero-length D2H Data FIS (i.e. Data FIS header immediately followed by CRC), and any D2H Data FIS
following a D2H Dma_Activate FIS are treated as unknown FIS types for all purposes.
23.5.3
Hot Plug Operation
Dynamic hot plug (such as surprise removal) is not supported in legacy mode.
However, using the PCS register configuration bits, and power management flows, a
device can be powered down by software, and the port can then be powered off,
allowing removal and insertion of a new device.
23.5.4
48-Bit (“Large”) LBA Operation Requirements
The SATA host controller supports 48-bit LBA through the host-to-device register FIS
when accesses are performed via writes to the task file. The SATA host controller will
ensure that the correct data is put into the correct byte of the host-to-device FIS as
follows: if only one write is performed, the data goes to the location specified; if a
second write is performed, the data from the first write is shifted into the “upper”
location, and the data from the second write goes to the location specified.
Suppose a sequence of writes occurred to the taskfile as follows:
• 1f2h (Sector Count)- 21h
• 1f2h (Sector Count) - 22h
• 1f3h (Sector Number - 31h
• 1f3h (Sector Number) - 32h
• 1f4h (Cylinder Low) - 41h
• 1f4h (Cylinder Low) - 42h
• 1f5h (Cylinder High) - 51h
• 1f5h (Cylinder High) - 52h
The resulting FIS when the command or control register is written will have the
following values:
Intel^® EP80579 Integrated Processor Product Line Datasheet
878
August 2009
Order Number: 320066-003US