EP80579 Datasheet, PDF (1198/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 33-32. Offset 08h: GISR - General Interrupt Status Register (Sheet 2 of 2)
Description:
View: IA F
Base Address: Base (IO)
Offset Start: 08h
Offset End: 08h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
01
00
Bit Acronym
Bit Description
Sticky
NMIACT
SERIRQACT
Watchdog Timer NMI Interrupt Active (1st Stage):
This bit is set when the first Stage of the 35-bit Down
Counter Reaches zero. An NMI interrupt is generated if
WDT_INT_TYPE is configured to do so (See WDT
Configuration Register).
This is a sticky bit and is only cleared by writing a ‘1’.
0 = No Interrupt
1 = Interrupt Active
Note: This bit is not set in free running mode.
Watchdog Timer SERIRQ Interrupt Active (1st
Stage): This bit is set when the first Stage of the 35-bit
Down Counter Reaches zero. An SERIRQ interrupt is
generated if WDT_INT_TYPE is configured to do so (See
WDT Configuration Register).
This is a sticky bit and is only cleared by writing a ‘1’.
0 = No Interrupt
1 = Interrupt Active
Note: This bit is not set in free running mode.
Bit Reset
Value
0h
0h
Bit Access
RWC
RWC
33.6.2.8 Offset 0Ch: RR0 - Reload Register 0
Table 33-33. Offset 0Ch: RR0 - Reload Register 0
Description:
View: IA F
Base Address: Base (IO)
Size: 8 bit
Default: 00h
Bit Range
07 : 00
Bit Acronym
Bit Description
Reserved ^{Reserved. Must be programmed to 0.}
Offset Start: 0Ch
Offset End: 0Ch
Power Well: Core
Sticky
Bit Reset
Value
Bit Access
00h
Intel^® EP80579 Integrated Processor Product Line Datasheet
1198
August 2009
Order Number: 320066-003US