EP80579 Datasheet, PDF (781/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
20.5.3
20.5.4
In these cases, the peripheral wishes to stop further DMA activity. It may do so by
sending an LDRQ# message with the ACT bit as ‘0’. However, since the DMA request
was seen, there is no guarantee that the cycle hasn’t been granted and runs on LPC.
Therefore, peripherals must take into account that a DMA cycle may still occur. The
peripheral can choose not to respond to this cycle, in which case the host aborts it, or it
can choose to complete the cycle normally with any random data.
This method of DMA deassertion must be prevented whenever possible in order to limit
boundary conditions both on the IICH and the peripheral.
The LDREQ DMA abort scheme should not be used if a transfer is in progress (a cycle
has started) and more than one transfer has been completed. In these cases, the
peripheral must use the SYNC field encoding 0000.
General Flow of DMA Transfers
Arbitration for DMA channels is performed through the 8237 within the host. Once the
host has won arbitration on behalf of a DMA channel assigned to LPC, it asserts
LFRAME# on the LPC Interface and begins the DMA transfer. The general flow for a
basic DMA transfer is as follows:
1. The IICH starts the transfer by asserting ‘0000b’ on LAD[3:0] with LFRAME#
asserted.
2. The IICH asserts ‘cycle type’ of DMA. The direction is based on the DMA transfer
direction.
3. The IICH asserts the channel number and, if applicable, terminal count.
4. The IICH indicates the size of the transfer; 8 or 16 bits.
5. If a DMA reads:
a. The IICH drives the first 8 bits of data and turns the bus around.
b. The peripheral acknowledges the data with a valid SYNC.
c. If a 16 bit transfer, the process is repeated for the next 8 bits.
6. If a DMA writes:
a. The IICH turns the bus around and waits for data.
b. The peripheral indicates data ready through SYNC and transfers the first byte.
c. If a 16-bit transfer, the peripheral indicates data ready and transfers the next
byte.
7. The peripheral turns around the bus.
Terminal Count
Terminal count is communicated through LAD[03] on the same clock that DMA channel
is communicated on LAD[02:00]. This field is the CHANNEL field. Terminal count
indicates the last byte of transfer, based upon the size of the transfer.
For example, on an 8-bit transfer size (SIZE field is ‘00b’), if the TC bit is set, then this
is the last byte. On a 16-bit transfer (SIZE field is ‘01b’), if the TC bit is set, then the
second byte is the last byte. The peripheral, therefore, must internalize the TC bit when
the CHANNEL field is communicated and only signal TC when the last byte of that
transfer size has been transferred.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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