EP80579 Datasheet, PDF (549/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.4.1.33 Offset 51h: PMNPTR - Power Management Next Capabilities Pointer
Register
This register identifies the capability structure and points to the next structure.
Table 16-172.Offset 51h: PMNPTR - Power Management Next Capabilities Pointer Register
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 51h
Offset End: 51h
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 51h
Offset End: 51h
Size: 8 bit
Default: 58h
Power Well: Core
Bit Range Bit Acronym
Bit Description
07 : 00
NCR
Next Capability Pointer: This field points to the next
Capability ID in this device which is the MSI.
Sticky
Bit Reset
Value
Bit Access
58h
RO
16.4.1.34 Offset 52h: PMCAPA - Power Management Capabilities
Register
This register identifies the capabilities for PM.
Table 16-173.Offset 52h: PMCAPA - Power Management Capabilities Register (Sheet 1 of
2)
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 52h
Offset End: 53h
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 52h
Offset End: 53h
Size: 16 bit
Default: C822h
Power Well: Core
Bit Range Bit Acronym
Bit Description
Sticky
15 : 11
PME Support: Identifies power states which assert PME.
Bits 15, 14 and 11 must be set to '1' for PCI-PCI bridge
structures representing ports on root complexes. The
definition of these bits is taken from the PCI Bus Power
Management Interface Specification Revision 1.1.
bit(11) XXXX1b PME# can be asserted from D0
bit(12) XXX1Xb
PME# can be asserted from D1
(IMCH does not support)
PMES_PMCAPA ^{bit(13) XX1XXb}
PME# can be asserted from D2
(IMCH does not support)
bit(14) X1XXXb PME# can be asserted from D3 hot
(IMCH does not support)
bit(15) 1XXXXb PME# can be asserted from D3 cold
(IMCH does not support)
Bit Reset
Value
11001b
Bit Access
RO
Note: D3 is not supported, default value shows incorrect
support for D3
10
D2S
D2 Support: This bit is hardwired to ‘0’ to Indicate the
power management state D2 is not supported.
09
D1S
D1 Support: This bit is hardwired to ‘0’ to Indicate the
power management state D1 is not supported.
0b
RO
0b
RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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