EP80579 Datasheet, PDF (1261/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
35.7
Gigabit Ethernet MAC I/O Spaces: Bus M, Device 0-2,
Function 0
The PCI-to-PCI Bridge implements IOADDR and IODATA registers in IA I/O space to
allow access to Gigabit MAC structures through the IOBAR of a Gigabit MAC (see
Section 35.6.1.11, “Offset 14h: IOBAR – CSR I/O Mapped BAR Register” on
page 1247). These registers are used to indirectly access Gigabit MAC structures before
the entire system memory map is available to use the MEMBAR. There are two
registers for each MAC
During an EEPROM read the configuration space will stall any configuration read or
write cycles until after the EEPROM read has completed. MEM/IO transfers generate an
AIOC internal bus command and it is up to the Gig to stall the transfer.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1261